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2012-10-12Use a transposed algorithm for handleMove().Jakob Stoklund Olesen
Completely update one interval at a time instead of collecting live range fragments to be updated. This avoids building data structures, except for a single SmallPtrSet of updated intervals. Also share code between handleMove() and handleMoveIntoBundle(). Add support for moving dead defs across other live values in the interval. The MI scheduler can do that. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165824 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-12Fix coalescing with IMPLICIT_DEF values.Jakob Stoklund Olesen
PHIElimination inserts IMPLICIT_DEF instructions to guarantee that all PHI predecessors have a live-out value. These IMPLICIT_DEF values are not considered to be real interference when coalescing virtual registers: %vreg1 = IMPLICIT_DEF %vreg2 = MOV32r0 When joining %vreg1 and %vreg2, the IMPLICIT_DEF instruction and its value number should simply be erased since the %vreg2 value number now provides a live-out value for the PHI predecesor block. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165813 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-12Fix big-endian codegen bug in DAGTypeLegalizer::ExpandRes_BITCASTUlrich Weigand
On PowerPC, a bitcast of <16 x i8> to i128 may run through a code path in ExpandRes_BITCAST that attempts to do an intermediate bitcast to a <4 x i32> vector, and then construct the Hi and Lo parts of the resulting i128 by pairing up two of those i32 vector elements each. The code already recognizes that on a big-endian system, the first two vector elements form the Hi part, and the final two vector elements form the Lo part (vice-versa from the little-endian situation). However, we also need to take endianness into account when forming each of those separate pairs: on a big-endian system, vector element 0 is the *high* part of the pair making up the Hi part of the result, and vector element 1 is the low part of the pair. The code currently always uses vector element 0 as the low part and vector element 1 as the high part, as is appropriate for little-endian platforms only. This patch fixes this by swapping the vector elements as they are paired up as appropriate. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165802 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-12Legalizer optimize a pair of div / mod to a call to divrem libcall if they areEvan Cheng
not legal. However, it should use a div instruction + mul + sub if divide is legal. The rem legalization code was missing a check and incorrectly uses a divrem libcall even when div is legal. rdar://12481395 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165778 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-11Remove unnecessary classof()'sSean Silva
isa<> et al. automatically infer when the cast is an upcast (including a self-cast), so these are no longer necessary. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165767 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-11Revert 165732 for further review.Micah Villmow
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165747 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-11Add in the first iteration of support for llvm/clang/lldb to allow variable ↵Micah Villmow
per address space pointer sizes to be optimized correctly. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165726 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-11Pass an explicit operand number to addLiveIns.Jakob Stoklund Olesen
Not all instructions define a virtual register in their first operand. Specifically, INLINEASM has a different format. <rdar://problem/12472811> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165721 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-11Follow the same routine to add target float expansion hookMichael Liao
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165707 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-11misched: Handle "transient" non-instructions.Andrew Trick
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165701 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-10Add a new interface to allow IR-level passes to access codegen-specific ↵Nadav Rotem
information. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165665 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-10Add in support for expansion of all of the comparison operations to the ↵Micah Villmow
absolute minimum required set. This allows a backend to expand any arbitrary set of comparisons as long as a minimum set is supported. The minimum set of required instructions is ISD::AND, ISD::OR, ISD::SETO(or ISD::SETOEQ) and ISD::SETUO(or ISD::SETUNE). Everything is expanded into one of two patterns: Pattern 1: (LHS CC1 RHS) Opc (LHS CC2 RHS) Pattern 2: (LHS CC1 LHS) Opc (RHS CC2 RHS) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165655 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-10Add alternative support for FP_ROUND from v2f32 to v2f64Michael Liao
- Due to the current matching vector elements constraints in ISD::FP_EXTEND, rounding from v2f32 to v2f64 is scalarized. Add a customized v2f32 widening to convert it into a target-specific X86ISD::VFPEXT to work around this constraints. This patch also reverts a previous attempt to fix this issue by recovering the scalarized ISD::FP_EXTEND pattern and thus significantly reduces the overhead of supporting non-power-2 vector FP extend. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165625 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-10Issue description:Stepan Dyatkovskiy
SchedulerDAGInstrs::buildSchedGraph ignores dependencies between FixedStack objects and byval parameters. So loading byval parameters from stack may be inserted *before* it will be stored, since these operations are treated as independent. Fix: Currently ARMTargetLowering::LowerFormalArguments saves byval registers with FixedStack MachinePointerInfo. To fix the problem we need to store byval registers with MachinePointerInfo referenced to first the "byval" parameter. Also commit adds two new fields to the InputArg structure: Function's argument index and InputArg's part offset in bytes relative to the start position of Function's argument. E.g.: If function's argument is 128 bit width and it was splitted onto 32 bit regs, then we got 4 InputArg structs with same arg index, but different offset values. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165616 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-10Remove the final bits of Attributes being declared in the AttributeBill Wendling
namespace. Use the attribute's enum value instead. No functionality change intended. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165610 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-10My earlier "fix" for PBQP (see r165201) was incorrect. The real issue was thatLang Hames
checkRegMaskInterference only initializes the bitmask on the first interference. This fixes PR14027 and (re)fixes PR13945. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165608 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-10misched: fall-back to a target hook for instr bundles.Andrew Trick
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165606 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-10misched: Use the TargetSchedModel interface wherever possible.Andrew Trick
Allows the new machine model to be used for NumMicroOps and OutputLatency. Allows the HazardRecognizer to be disabled along with itineraries. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165603 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-09misched: Add computeInstrLatency to TargetSchedModel.Andrew Trick
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165566 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-09misched: Allow flags to disable hasInstrSchedModel/hasInstrItineraries for ↵Andrew Trick
external users of TargetSchedule. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165564 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-09misched: Remove LoopDependencies heuristic.Andrew Trick
This wasn't contributing anything significant to postRA heuristics except compile time (by my measurements) and will be replaced by a more general heuristic for cross-region dependencies within the scheduler itself. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165563 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-09Use the attribute enums to query if a parameter has an attribute.Bill Wendling
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165550 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-09Add in the first step of the multiple pointer support. This adds in support ↵Micah Villmow
to the data layout for specifying a per address space pointer size. The next step is to update the optimizers to allow them to optimize the different address spaces with this information. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165505 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-09Create enums for the different attributes.Bill Wendling
We use the enums to query whether an Attributes object has that attribute. The opaque layer is responsible for knowing where that specific attribute is stored. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165488 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-08Fix up comment to be more clear.Eric Christopher
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165463 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-08Refactor the AddrMode class out of TLI to its own header file.Nadav Rotem
This class is used by LSR and a number of places in the codegen. This is the first step in de-coupling LSR from TLI, and creating a new interface in between them. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165455 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-08Don't crash on extra evil irreducible control flow.Jakob Stoklund Olesen
When the CFG contains a loop with multiple entry blocks, the traces computed by MachineTraceMetrics don't always have the same nice properties. Loop back-edges are normally excluded from traces, but MachineLoopInfo doesn't recognize loops with multiple entry blocks, so those back-edges may be included. Avoid asserting when that happens by adding an isEarlierInSameTrace() function that accurately determines if a dominating block is part of the same trace AND is above the currrent block in the trace. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165434 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-08Fixup comment.Eric Christopher
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165427 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-08Fixup comments.Eric Christopher
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165426 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-08misched: remove the unused getSpecialAddressLatency hook.Andrew Trick
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165418 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-08misched: remove forceUnitLatencies. Defaults are handled by the default ↵Andrew Trick
SchedModel git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165417 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-08misched: avoid scheduling an instruction twice.Andrew Trick
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165416 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-08Move TargetData to DataLayout.Micah Villmow
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165402 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-07Remove unused MachineInstr constructors that don't take a DebugLoc argument.Craig Topper
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165382 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-07Fix indentation. Remove 'else' after return. No functional change.Craig Topper
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165381 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-05Remove unused but set variable flagged by GCC.Benjamin Kramer
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165331 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-05Simplify code, don't or a bool with an uint64_t.Benjamin Kramer
No functionality change. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165321 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-04When merging connsecutive stores, use vectors to store the constant zero.Nadav Rotem
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165267 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-04Update this a bit more to represent how the prologue should work:Eric Christopher
a) frame setup instructions define the prologue b) we shouldn't change our location mid-stream Add a test to make sure that the stack adjustment stays within the prologue. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165250 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-04Get MCSchedModel directly from the subtarget.Jakob Stoklund Olesen
Not all targets have itineraries, but the subtarget always has an MCSchedModel. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165236 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-04Switch MachineTraceMetrics to the new TargetSchedModel interface.Jakob Stoklund Olesen
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165235 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-04Fix reg mask slot test, and preserve LiveIntervals and VirtRegMap in the PBQPLang Hames
allocator. Fixes PR13945. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165201 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-04Enable -schedmodel, but prefer itineraries until we have more benchmark data.Andrew Trick
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165188 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-03Update to use the predicate methods to query if an attribute exists.Bill Wendling
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165163 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-03Fix a cycle in the DAG. In this code we replace multiple loads with a single ↵Nadav Rotem
load and multiple stores with a single load. We create the wide loads and stores (and their chains) before we remove the scalar loads and stores and fix the DAG chain. We attempted to merge loads with a different chain. When that happened, the assumption that it is safe to RAUW broke and a cycle was introduced. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165148 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-03A DAGCombine optimization for mergeing consecutive stores to memory. The ↵Nadav Rotem
optimization is not profitable in many cases because modern processors perform multiple stores in parallel and merging stores prior to merging requires extra work. We handle two main cases: 1. Store of multiple consecutive constants: q->a = 3; q->4 = 5; In this case we store a single legal wide integer. 2. Store of multiple consecutive loads: int a = p->a; int b = p->b; q->a = a; q->b = b; In this case we load/store either ilegal vector registers or legal wide integer registers. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165125 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-03Fixed a bug in the ExecutionDependencyFix pass that caused dependencies to ↵Silviu Baranga
not propagate through implicit defs. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165102 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-03Revert 165051-165049 while looking into the foreach.m failure inEric Christopher
more detail. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165099 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-03The early if conversion pass is ready to be used as an opt-in.Jakob Stoklund Olesen
Enable the pass by default for targets that request it, and change the -enable-early-ifcvt to the opposite -disable-early-ifcvt. There are still some x86 regressions when enabling early if-conversion because of the missing machine models. Disable the pass for x86 until machine models are added. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165075 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-02Revert "Don't use a debug location for frame setup instructions in the"Eric Christopher
This reverts 165055 and 165052 temporarily while I look at debugger failures. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165071 91177308-0d34-0410-b5e6-96231b3b80d8
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