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operands may be the same. PR7018. rdar://7939869.
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SSAUpdater for the value from the first def may see uses of undefined values,
because the later defs will not have been updated yet.
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Based on a patch by Javier Martinez.
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namespace etc..
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and not the real problem itself, by dropping debug info for i128 values.
rdar://7958162.
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getConstantFP to accept the two supported long double
target types. This was not the original intent, but
there are other places that assume this works and it's
easy enough to do.
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patch by Peter Housel!
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lowered copies.
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increase in the debug line info section, and it's causing
regressions in a gdb testsuite.
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doesn't have to guess.
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with the fix in 103157.
%reg1039:1<def> = VMOVS %S1<kill>, pred:14, pred:%reg0
is not coalescable since none of the super-registers of S1 are in reg1039's
register class: DPR_VFP2. But it is still a legal copy instruction so it should
not assert.
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twice!"' failed.
Users can write broken code that emits the same label twice with asm renaming,
detect this and emit a fatal backend error instead of aborting.
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support a new bottom-up mode.
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of just letting them inherit the debug locations of adjacent instructions.
Debug info should aim to be either accurate or absent.
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reg_sequence instructions that are formed by registers defined by distinct instructions. e.g.
80 %reg1041:6<def> = VSHRNv4i16 %reg1034<kill>, 12, pred:14, pred:%reg0
. . .
120 %reg1041:5<def> = VSHRNv4i16 %reg1039<kill>, 12, pred:14, pred:%reg0
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MachineSSAUpdater to avoid duplicating all the code.
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references of the source operands with references of the destination with subreg indices. e.g.
%reg1029<def>, %reg1030<def> = VLD1q16 %reg1024<kill>, ...
%reg1031<def> = REG_SEQUENCE %reg1029<kill>, 5, %reg1030<kill>, 6
=>
%reg1031:5<def>, %reg1031:6<def> = VLD1q16 %reg1024<kill>, ...
PHI elimination now does more than phi elimination. It is really a de-SSA pass.
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available all the time.
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argument out of the entry block. rdar://7937489
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This should make it possible to start producing kill flags in isel without
breaking stuff.
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in registers into a separate function to de-couple it from the
top-down-specific logic in getRegForValue.
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RemoveCopyByCommutingDef().
This fixes PR6941.
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debug output is showing machine instructions, the IR-level basic block names
aren't very meaningful, and because multiple machine basic blocks may be
derived from one IR-level BB, they're also not unique.
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beneficial cases. See the changes in test/CodeGen/X86/tail-opts.ll and
test/CodeGen/ARM/ifcvt2.ll for details.
The fix is to change HashEndOfMBB to hash at most one instruction,
instead of trying to apply heuristics about when it will be profitable to
consider more than one instruction. The regular tail-merging heuristics
are already prepared to handle the same cases, and they're more precise.
Also, make test/CodeGen/ARM/ifcvt5.ll and
test/CodeGen/Thumb2/thumb2-branch.ll slightly more complex so that they
continue to test what they're intended to test.
And, this eliminates the problem in
test/CodeGen/Thumb2/2009-10-15-ITBlockBranch.ll, the testcase from
PR5204. Update it accordingly.
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preventing the emission of the NOP on Darwin for a
function with no actual code. From timberwolfmc
with TEST=optllcdbg.
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when needed. This fixes PR7001
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handles argument lowering anyway, so there's no need for special
casing here.
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try to put a kill flag on a DBG_INFO instruction.
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Seen in SingleSrc/Benchmarks/Misc/flops with TEST=optllcdbg.
7929951.
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