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easy cases.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102678 91177308-0d34-0410-b5e6-96231b3b80d8
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of different register classes. e.g.
%reg1048:3<def> = EXTRACT_SUBREG %RAX<kill>, 3
Where %reg1048 is a GR32 register. This is not impossible to handle, but it is
pretty hard and very rare.
This should unbreak the dragonegg builder.
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##DEBUG_VALUE: runOnMachineFunction:this <- RDI+0
##DEBUG_VALUE: runOnMachineFunction:fn <- RSI+0
##DEBUG_VALUE: DeadDefs <- undef ## SimpleRegisterCoalescing.cpp:2706
##DEBUG_VALUE: getRegInfo:this <- [%rsp+$56]+$0
##DEBUG_VALUE: getTarget:this <- [%rsp+$56]+$0
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entry block.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102653 91177308-0d34-0410-b5e6-96231b3b80d8
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102584 91177308-0d34-0410-b5e6-96231b3b80d8
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entry block.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102573 91177308-0d34-0410-b5e6-96231b3b80d8
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- Also, update dbg_value is the value is being re-matted from a frame slot, e.g. fixed slots for arguments.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102565 91177308-0d34-0410-b5e6-96231b3b80d8
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instructions for function arguments early and insert them after instruction selection is done.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102554 91177308-0d34-0410-b5e6-96231b3b80d8
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Before:
DBG_VALUE %RSI, 0, !-1; dbg:SimpleRegisterCoalescing.cpp:2707
Now:
DBG_VALUE %RSI, 0, !"this"; dbg:SimpleRegisterCoalescing.cpp:2707
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102518 91177308-0d34-0410-b5e6-96231b3b80d8
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alignment of globals to the preferred alignment, but only when
there is no section specified on the global (by far the common
case).
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matching llvm.dbg.declare intrinsic is missing.
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update them. Computing kill flags is notoriously difficult, and the coalescer
would get it wrong sometimes, and it would completely skip physical registers.
Now we simply remove kill flags based on the live intervals after coalescing.
This is a few percent slower, but now we get correct kill flags for physical
registers after coalescing.
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failed to do anything.
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ForcedAlignBits argument, tweaking the single client of it.
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- Catch more further dag combine opportunities as result of operand promotion, e.g. (i32 anyext (i16 trunc (i32 x))) -> (i32 x)
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Emit such ranges using DW_AT_ranges.
This patch fixes bug (PR6894) introduced by previous version of this patch.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102453 91177308-0d34-0410-b5e6-96231b3b80d8
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should fix some "g++.dg-struct-layout-1" failures,
rdar://7886017
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of the dbg testsuite regressions. I don't think this is
really the right fix; this change exposed an existing problem
upstream somewhere.
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otherwise labels get incorrectly merged. We handled this by emitting a
".byte 0", but this isn't correct on thumb/arm targets where the text segment
needs to be a multiple of 2/4 bytes. Handle this by emitting a noop. This
is more gross than it should be because arm/ppc are not fully mc'ized yet.
This fixes rdar://7908505
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to print the operand.
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simplifies debug range entries.
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produces a comment on targets that support it, but
the Dwarf writer is not hooked up yet.
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function arguments).
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alignment of globals with a specified alignment, we fix
common variables to obey their alignment. Add a comment
explaining why this behavior is important.
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indices when the live interval are being re-materialized.
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SSAUpdater. I'm going to try to refactor this to share most of the code
between them.
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and rename it to emitFrameIndexDebugValue.
- Teach spiller to modify DBG_VALUE instructions to reference spill slots.
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