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2008-03-10Give TargetLowering::getSetCCResultType() a parameter so that ISD::SETCC'sScott Michel
return ValueType can depend its operands' ValueType. This is a cosmetic change, no functionality impacted. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48145 91177308-0d34-0410-b5e6-96231b3b80d8
2008-03-10Minor cleanup. No functionality change.Bill Wendling
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48142 91177308-0d34-0410-b5e6-96231b3b80d8
2008-03-10- Fix a subtle bug in RemoveCopyByCommutingDef. ALR is the live range where ↵Evan Cheng
the source is defined; BLR is the live range which is defined by the copy. If ALR and BLR overlaps and end of BLR extends beyond end of ALR, e.g. A = or A, B ... B = A ... C = A<kill> ... = B then do not add kills of A to the newly created B interval. - Also fix some kill info update bug. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48141 91177308-0d34-0410-b5e6-96231b3b80d8
2008-03-10DohEvan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48140 91177308-0d34-0410-b5e6-96231b3b80d8
2008-03-10Move StrongPHIElimination after live interval analysis. This will make ↵Owen Anderson
things happier down the road. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48138 91177308-0d34-0410-b5e6-96231b3b80d8
2008-03-10Avoid creating BUILD_VECTOR of all zero elements of "non-normalized" type ↵Evan Cheng
(e.g. v8i16 on x86) after legalizer. Instruction selection does not expect to see them. In all likelihood this can only be an issue in a bugpoint reduced test case. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48136 91177308-0d34-0410-b5e6-96231b3b80d8
2008-03-10Allow insert_subreg into implicit, target-specific values. Christopher Lamb
Change insert/extract subreg instructions to be able to be used in TableGen patterns. Use the above features to reimplement an x86-64 pseudo instruction as a pattern. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48130 91177308-0d34-0410-b5e6-96231b3b80d8
2008-03-10Increase ISD::ParamFlags to 64 bits. Increase the ByValSizeDale Johannesen
field to 32 bits, thus enabling correct handling of ByVal structs bigger than 0x1ffff. Abstract interface a bit. Fixes gcc.c-torture/execute/pr23135.c and gcc.c-torture/execute/pr28982b.c in gcc testsuite (were ICE'ing on ppc32, quietly producing wrong code on x86-32.) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48122 91177308-0d34-0410-b5e6-96231b3b80d8
2008-03-09remove an extraneous (and ugly) default argument, thanks Duncan.Chris Lattner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48117 91177308-0d34-0410-b5e6-96231b3b80d8
2008-03-09fp_round's produced by getCopyFromParts should always be exact, becauseChris Lattner
they are produced by calls (which are known exact) and by cross block copies which are known to be produced by extends. This improves: define double @test2() { %tmp85 = call double asm sideeffect "fld0", "={st(0)}"() ret double %tmp85 } from: _test2: subl $20, %esp # InlineAsm Start fld0 # InlineAsm End fstpl 8(%esp) movsd 8(%esp), %xmm0 movsd %xmm0, (%esp) fldl (%esp) addl $20, %esp #FP_REG_KILL ret to: _test2: # InlineAsm Start fld0 # InlineAsm End #FP_REG_KILL ret by avoiding a f64 <-> f80 trip git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48108 91177308-0d34-0410-b5e6-96231b3b80d8
2008-03-09teach X86InstrInfo::copyRegToReg how to copy into ST(0) from Chris Lattner
an RFP register class. Teach ScheduleDAG how to handle CopyToReg with different src/dst reg classes. This allows us to compile trivial inline asms that expect stuff on the top of x87-fp stack. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48107 91177308-0d34-0410-b5e6-96231b3b80d8
2008-03-09Add ScheduleDAG support for copytoreg where the src/dst register areChris Lattner
in different register classes, e.g. copy of ST(0) to RFP*. This gets some really trivial inline asm working that plops things on the top of stack (PR879) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48105 91177308-0d34-0410-b5e6-96231b3b80d8
2008-03-09fix 80 col violationChris Lattner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48100 91177308-0d34-0410-b5e6-96231b3b80d8
2008-03-09extend fp values with FP_EXTEND not FP_ROUND.Chris Lattner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48097 91177308-0d34-0410-b5e6-96231b3b80d8
2008-03-09Fix two problems in SelectionDAGLegalize::ExpandBUILD_VECTOR's handlingChris Lattner
of BUILD_VECTORS that only have two unique elements: 1. The previous code was nondeterminstic, because it walked a map in SDOperand order, which isn't determinstic. 2. The previous code didn't handle the case when one element was undef very well. Now we ensure that the generated shuffle mask has the undef vector on the RHS (instead of potentially being on the LHS) and that any elements that refer to it are themselves undef. This allows us to compile CodeGen/X86/vec_set-9.ll into: _test3: movd %rdi, %xmm0 punpcklqdq %xmm0, %xmm0 ret instead of: _test3: movd %rdi, %xmm1 #IMPLICIT_DEF %xmm0 punpcklqdq %xmm1, %xmm0 ret ... saving a register. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48060 91177308-0d34-0410-b5e6-96231b3b80d8
2008-03-08Teach SD some vector identities, allowing us to compile vec_set-9 into:Chris Lattner
_test3: movd %rdi, %xmm1 #IMPLICIT_DEF %xmm0 punpcklqdq %xmm1, %xmm0 ret instead of: _test3: #IMPLICIT_DEF %rax movd %rax, %xmm0 movd %rdi, %xmm1 punpcklqdq %xmm1, %xmm0 ret This is still not ideal. There is no reason to two xmm regs. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48058 91177308-0d34-0410-b5e6-96231b3b80d8
2008-03-08Implement x86 support for @llvm.prefetch. It corresponds to prefetcht{0|1|2} ↵Evan Cheng
and prefetchnta instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48042 91177308-0d34-0410-b5e6-96231b3b80d8
2008-03-07Something that kills a super-register alsoBill Wendling
kills the sub-register. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48038 91177308-0d34-0410-b5e6-96231b3b80d8
2008-03-07Fixed a register scavenger bug. If a def is re-defining part of a super ↵Evan Cheng
register, there must be an implicit def of the super-register on the MI. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48024 91177308-0d34-0410-b5e6-96231b3b80d8
2008-03-06When setting the "unused" info, take into account something like this:Bill Wendling
%r3<def> = OR %x3<kill>, %x3 We don't want to mark the %r3 as unused even though it's a sub-register of %x3. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48003 91177308-0d34-0410-b5e6-96231b3b80d8
2008-03-0680 col violation.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47998 91177308-0d34-0410-b5e6-96231b3b80d8
2008-03-06some more spelling changesGabor Greif
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47996 91177308-0d34-0410-b5e6-96231b3b80d8
2008-03-06Constant fold SIGN_EXTEND_INREG with ashr not lshr.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47992 91177308-0d34-0410-b5e6-96231b3b80d8
2008-03-05Fix a coalescer bug wrt how dead copy interval is shortened.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47966 91177308-0d34-0410-b5e6-96231b3b80d8
2008-03-05Clarify that CALLSEQ_START..END may not be nested,Dale Johannesen
and add some protection against creating such. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47957 91177308-0d34-0410-b5e6-96231b3b80d8
2008-03-05Generalize FP constant shrinking optimization to apply to any vtChris Lattner
except ppc long double. This allows us to shrink constant pool entries for x86 long double constants, which in turn allows us to use flds/fldl instead of fldt. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47938 91177308-0d34-0410-b5e6-96231b3b80d8
2008-03-05Improve comment, pass in the original VT so that we can shrink a long double ↵Chris Lattner
constant all the way to float, not stopping at double. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47937 91177308-0d34-0410-b5e6-96231b3b80d8
2008-03-05Codegen support for i128 UINT_TO_FP. This just fixes aDan Gohman
bug in r47928 (Int64Ty is the correct type for the constant pool entry here) and removes the asserts, now that the code is capable of handling i128. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47932 91177308-0d34-0410-b5e6-96231b3b80d8
2008-03-05Add a target lowering hook to control whether it's worthwhile to compress fp ↵Evan Cheng
constant. For x86, if sse2 is available, it's not a good idea since cvtss2sd is slower than a movsd load and it prevents load folding. On x87, it's important to shrink fp constant since fldt is very expensive. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47931 91177308-0d34-0410-b5e6-96231b3b80d8
2008-03-0564bit CAS on 32bit x86.Andrew Lenharth
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47929 91177308-0d34-0410-b5e6-96231b3b80d8
2008-03-05Codegen support for i128 SINT_TO_FP.Dan Gohman
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47928 91177308-0d34-0410-b5e6-96231b3b80d8
2008-03-05Refactor code. Remove duplicated functions that basically do the same thing asEvan Cheng
findRegisterUseOperandIdx, findRegisterDefOperandIndx. Fix some naming inconsistencies. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47927 91177308-0d34-0410-b5e6-96231b3b80d8
2008-03-04Some improvements related to the computation of heights, depths of SUnits.Roman Levenstein
The basic idea is that all these algorithms are computing the longest paths from the root node or to the exit node. Therefore the existing implementation that uses and iterative and potentially exponential algorithm was changed to a well-known graph algorithm based on dynamic programming. It has a linear run-time. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47884 91177308-0d34-0410-b5e6-96231b3b80d8
2008-03-04Refactor ExpandConstantFP so it can optimize load from constpool of types ↵Evan Cheng
larger than f64 into extload from smaller types. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47883 91177308-0d34-0410-b5e6-96231b3b80d8
2008-03-04Did I say 'e = getNumOperands()'? I meant --e, of course.Bill Wendling
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47875 91177308-0d34-0410-b5e6-96231b3b80d8
2008-03-04Rename isOperand() to isOperandOf() (and other similar methods). It always ↵Evan Cheng
confuses me. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47872 91177308-0d34-0410-b5e6-96231b3b80d8
2008-03-03Miscellaneous clean-ups based on Evan's feedback:Bill Wendling
- Cleaned up how the prologue-epilogue inserter loops over the instructions. - Instead of restarting the processing of an instruction if we remove an implicit kill, just update the end iterator and make sure that the iterator isn't incremented. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47870 91177308-0d34-0410-b5e6-96231b3b80d8
2008-03-03Misc. APInt-ification in the DAGCombiner.Dan Gohman
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47869 91177308-0d34-0410-b5e6-96231b3b80d8
2008-03-03More APInt-ification.Dan Gohman
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47868 91177308-0d34-0410-b5e6-96231b3b80d8
2008-03-03Yet more APInt-ification.Dan Gohman
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47867 91177308-0d34-0410-b5e6-96231b3b80d8
2008-03-03More APInt-ification.Dan Gohman
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47866 91177308-0d34-0410-b5e6-96231b3b80d8
2008-03-03More APInt-ification.Dan Gohman
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47864 91177308-0d34-0410-b5e6-96231b3b80d8
2008-03-03Go through the machine instruction's operands to make sure that we're notBill Wendling
marking both a super- and sub-register as "killed". This removes implicit uses that are marked as "killed". git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47862 91177308-0d34-0410-b5e6-96231b3b80d8
2008-03-03Make the register scavenger update the bookkeeping values for sub/superBill Wendling
registers. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47861 91177308-0d34-0410-b5e6-96231b3b80d8
2008-03-03Multiple instructions can be inserted when eliminating frame indexes. We needBill Wendling
the register scavenger to process all of those new instructions instead of just the last one inserted. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47860 91177308-0d34-0410-b5e6-96231b3b80d8
2008-03-01all but CAS working on x86Andrew Lenharth
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47798 91177308-0d34-0410-b5e6-96231b3b80d8
2008-03-01Add MVT::is128BitVector and is64BitVector. ShrinkDale Johannesen
unaligned load/store code using them. Per review of unaligned load/store vector patch. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47782 91177308-0d34-0410-b5e6-96231b3b80d8
2008-03-01Refactor / clean up code; remove td list scheduler special tie breaker (no ↵Evan Cheng
real benefit). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47779 91177308-0d34-0410-b5e6-96231b3b80d8
2008-02-29Don't fill eh frames even though these are text sections.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47765 91177308-0d34-0410-b5e6-96231b3b80d8
2008-02-29If we reload a virtual register that's already been assigned, we want to markBill Wendling
that instruction as its "last use". This fixes PR1925. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47758 91177308-0d34-0410-b5e6-96231b3b80d8