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into MachineInstrs. This is mostly just moving the code from
ScheduleDAGSDNodesEmit.cpp into a new class. This decouples MachineInstr
emitting from scheduling.
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since it won't do any folding. This will help avoid some inconvenient
casting.
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it isn't needed in the ScheduleDAGSDNodes schedulers.
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is trivially rematerializable and integrate it into
TargetInstrInfo::isTriviallyReMaterializable. This way, all places that
need to know whether an instruction is rematerializable will get the
same answer.
This enables the useful parts of the aggressive-remat option by
default -- using AliasAnalysis to determine whether a memory location
is invariant, and removes the questionable parts -- rematting operations
with virtual register inputs that may not be live everywhere.
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alloca or llvm.dbg.declare location.
While recording beginning of a function, use scope info from the first location entry instead of just relying on first location entry itself.
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TargetInstrDesc::isRematerializable flag, so it isn't necessary to do
this check in its callers.
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information when unfolding memory references.
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optimized away. Eventually DwarfChecker will clean this up during llvm verification stage.
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licm'ed out of loop.
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similar to getTargetExtractSubreg.
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has arguments. Extra line number entries trip gdb in some cases.
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to declare that they preserve other passes without needing to pull in
additional header file or library dependencies. Convert MachineFunctionPass
and CodeGenLICM to make use of this.
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but are allocated by the scavenger. The re-use algorithm needs to watch for that.
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what's up.
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going to have the time
to finish it any time soon. If someone's interested it, they can resurrect it from SVN history.
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teach it how to recognize invariant physical registers.
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implementations with a new MachineInstr::isInvariantLoad, which uses
MachineMemOperands and is target-independent. This brings MachineLICM
and other functionality to targets which previously lacked an
isInvariantLoad implementation.
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a virtual register to eliminate a frame index, it can return that register
and the constant stored there to PEI to track. When scavenging to allocate
for those registers, PEI then tracks the last-used register and value, and
if it is still available and matches the value for the next index, reuses
the existing value rather and removes the re-materialization instructions.
Fancier tracking and adjustment of scavenger allocations to keep more
values live for longer is possible, but not yet implemented and would likely
be better done via a different, less special-purpose, approach to the
problem.
eliminateFrameIndex() is modified so the target implementations can return
the registers they wish to be tracked for reuse.
ARM Thumb1 implements and utilizes the new mechanism. All other targets are
simply modified to adjust for the changed eliminateFrameIndex() prototype.
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This is not yet enabled.
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verbose-asm mode, print comments instead. This eliminates a non-comment
difference between verbose-asm mode and non-verbose-asm mode.
Also, factor out the relevant code out of all the targets and into
target-independent code.
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where the element is of a basic builtin type. For example, to get
an i8* use getInt8PtrTy.
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and after printing an instruction.
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This will be used by processDebugLoc().
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This code is not yet enabled.
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check debug info's presence in a module.
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This can happen if debug info is processed lazily.
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void foo() { static int bar = 42; }
Here, foo's DIE is parent of bar's DIE.
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spill slot. When frame references are via the frame pointer, they will be
negative, but Thumb1 load/store instructions only allow positive immediate
offsets. Instead, Thumb1 will spill to R12.
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the new predicates I added) instead of going through a context and doing a
pointer comparison. Besides being cheaper, this allows a smart compiler
to turn the if sequence into a switch.
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which causes dependence info to be linked into lli.
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