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2007-04-29Implement review feedbackAnton Korobeynikov
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36564 91177308-0d34-0410-b5e6-96231b3b80d8
2007-04-28memory operands that have a direct operand should have their stores createdChris Lattner
before the copies into physregs are done. This avoids having flag operands skip the store, causing cycles in the dag at sched time. This fixes infinite loops on these tests: test/CodeGen/Generic/2007-04-08-MultipleFrameIndices.ll for PR1308 test/CodeGen/PowerPC/2007-01-29-lbrx-asm.ll test/CodeGen/PowerPC/2007-01-31-InlineAsmAddrMode.ll test/CodeGen/X86/2006-07-12-InlineAsmQConstraint.ll for PR828 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36547 91177308-0d34-0410-b5e6-96231b3b80d8
2007-04-28eliminate more redundant constraint type analysisChris Lattner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36546 91177308-0d34-0410-b5e6-96231b3b80d8
2007-04-28merge constraint type analysis stuff together.Chris Lattner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36545 91177308-0d34-0410-b5e6-96231b3b80d8
2007-04-28Significant refactoring of the inline asm stuff, to support future changes.Chris Lattner
No functionality change. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36544 91177308-0d34-0410-b5e6-96231b3b80d8
2007-04-28Implement review feedback. Aliasees can be either GlobalValue's orAnton Korobeynikov
bitcasts of them. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36537 91177308-0d34-0410-b5e6-96231b3b80d8
2007-04-28memory inputs to an inline asm are required to have an address available.Chris Lattner
If the operand is not already an indirect operand, spill it to a constant pool entry or a stack slot. This fixes PR1356 and CodeGen/X86/2007-04-27-InlineAsm-IntMemInput.ll git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36536 91177308-0d34-0410-b5e6-96231b3b80d8
2007-04-28Fix CodeGen/Generic/2007-04-27-LargeMemObject.ll andChris Lattner
CodeGen/Generic/2007-04-27-InlineAsm-X-Dest.ll git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36534 91177308-0d34-0410-b5e6-96231b3b80d8
2007-04-28Fix this to match change to InlineAsm class.Chris Lattner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36524 91177308-0d34-0410-b5e6-96231b3b80d8
2007-04-27Fix incorrect legalization of EHSELECTOR. This fixesChris Lattner
CodeGen/Generic/2007-04-14-EHSelectorCrash.ll and PR1326 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36510 91177308-0d34-0410-b5e6-96231b3b80d8
2007-04-27Expand UINT_TO_FP in turns of SINT_TO_FP when UINTTOFP_* libcalls are not ↵Evan Cheng
available. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36501 91177308-0d34-0410-b5e6-96231b3b80d8
2007-04-27improve EH global handling, patch by Duncan Sands.Chris Lattner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36499 91177308-0d34-0410-b5e6-96231b3b80d8
2007-04-26enable Anton's shift/and switch lowering stuff! It now passes ppc bootstrapChris Lattner
successfully! woohoo... git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36496 91177308-0d34-0410-b5e6-96231b3b80d8
2007-04-26Fixx off-by-one bug, which prevents llvm-gcc bootstrap on ppc32Anton Korobeynikov
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36490 91177308-0d34-0410-b5e6-96231b3b80d8
2007-04-26Fix a typo in a comment.Dan Gohman
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36485 91177308-0d34-0410-b5e6-96231b3b80d8
2007-04-26Rename findRegisterUseOperand to findRegisterUseOperandIdx to avoid confusion.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36483 91177308-0d34-0410-b5e6-96231b3b80d8
2007-04-26Minor bug.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36473 91177308-0d34-0410-b5e6-96231b3b80d8
2007-04-26Be careful when to add implicit kill / dead operands. Don't add them during ↵Evan Cheng
/ post reg-allocation. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36458 91177308-0d34-0410-b5e6-96231b3b80d8
2007-04-25Match MachineFunction::UsedPhysRegs changes.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36452 91177308-0d34-0410-b5e6-96231b3b80d8
2007-04-25Change UsedPhysRegs from array bool to BitVector to save some space. Setting ↵Evan Cheng
/ getting its states now go through MachineFunction. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36451 91177308-0d34-0410-b5e6-96231b3b80d8
2007-04-25Clean up.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36449 91177308-0d34-0410-b5e6-96231b3b80d8
2007-04-25Data structure change to improve compile time (especially in debug mode).Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36447 91177308-0d34-0410-b5e6-96231b3b80d8
2007-04-25This was lefted out. Fixed sumarray-dbl.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36445 91177308-0d34-0410-b5e6-96231b3b80d8
2007-04-25Implement aliases. This fixes PR1017 and it's dependent bugs. CFE partAnton Korobeynikov
will follow. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36435 91177308-0d34-0410-b5e6-96231b3b80d8
2007-04-25Fix for PR1306.Evan Cheng
- A register def / use now implicitly affects sub-register liveness but does not affect liveness information of super-registers. - Def of a larger register (if followed by a use later) is treated as read/mod/write of a smaller register. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36434 91177308-0d34-0410-b5e6-96231b3b80d8
2007-04-25Clean up.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36431 91177308-0d34-0410-b5e6-96231b3b80d8
2007-04-25support for >4G stack framesChris Lattner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36425 91177308-0d34-0410-b5e6-96231b3b80d8
2007-04-25support > 4G stack objectsChris Lattner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36422 91177308-0d34-0410-b5e6-96231b3b80d8
2007-04-25allow support for 64-bit stack objectsChris Lattner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36420 91177308-0d34-0410-b5e6-96231b3b80d8
2007-04-25Be more careful about folding op(x, undef) when we have vector operands.Chris Lattner
This fixes CodeGen/X86/2007-04-24-VectorCrash.ll git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36413 91177308-0d34-0410-b5e6-96231b3b80d8
2007-04-24Assertion when using a 1-element vector for an add operation. Get theBill Wendling
real vector type in this case. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36402 91177308-0d34-0410-b5e6-96231b3b80d8
2007-04-24Use '-1U' where '-1UL' is obvious overkill, eliminating gcc warnings aboutScott Michel
tests always being true in the process. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36387 91177308-0d34-0410-b5e6-96231b3b80d8
2007-04-23modify per review commentaryDale Johannesen
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36383 91177308-0d34-0410-b5e6-96231b3b80d8
2007-04-23make EmitAlignment work the way Chris says it shouldDale Johannesen
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36368 91177308-0d34-0410-b5e6-96231b3b80d8
2007-04-22PR400 phase 2. Propagate attributed load/store information through DAGs.Christopher Lamb
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36356 91177308-0d34-0410-b5e6-96231b3b80d8
2007-04-21X86 TLS: Implement review feedback.Lauro Ramos Venancio
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36318 91177308-0d34-0410-b5e6-96231b3b80d8
2007-04-21Revert Christopher Lamb's load/store alignment changes.Reid Spencer
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36309 91177308-0d34-0410-b5e6-96231b3b80d8
2007-04-21add support for alignment attributes on load/store instructionsChristopher Lamb
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36301 91177308-0d34-0410-b5e6-96231b3b80d8
2007-04-20Allow the lowering of ISD::GLOBAL_OFFSET_TABLE.Lauro Ramos Venancio
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36290 91177308-0d34-0410-b5e6-96231b3b80d8
2007-04-20Implement "general dynamic", "initial exec" and "local exec" TLS models forLauro Ramos Venancio
X86 32 bits. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36283 91177308-0d34-0410-b5e6-96231b3b80d8
2007-04-18VarInfo::UsedBlocks is no longer used. Remove.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36250 91177308-0d34-0410-b5e6-96231b3b80d8
2007-04-18allow SRL to simplify its operands, as it doesn't demand all bits as input.Chris Lattner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36245 91177308-0d34-0410-b5e6-96231b3b80d8
2007-04-18When replacing a node in SimplifyDemandedBits, if the old node used anyChris Lattner
single-use nodes, they will be dead soon. Make sure to remove them before processing other nodes. This implements CodeGen/X86/shl_elim.ll git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36244 91177308-0d34-0410-b5e6-96231b3b80d8
2007-04-18fix a pastoChris Lattner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36242 91177308-0d34-0410-b5e6-96231b3b80d8
2007-04-18Don't populate TryAgainList when coalescing only physical registers with ↵Evan Cheng
virtual registers. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36240 91177308-0d34-0410-b5e6-96231b3b80d8
2007-04-18Increment use count of new virtuals created during PHI elimination.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36233 91177308-0d34-0410-b5e6-96231b3b80d8
2007-04-17Fix a bug in my previous patch, grabbing the shift amount width from theChris Lattner
wrong operand. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36223 91177308-0d34-0410-b5e6-96231b3b80d8
2007-04-17Fold (x << c1)>> c2 into a single shift if the bits shifted out aren't used.Chris Lattner
This compiles: int baz(long long a) { return (short)(((int)(a >>24)) >> 9); } into: _baz: srwi r2, r3, 1 extsh r3, r2 blr on PPC, instead of: _baz: slwi r2, r3, 8 srwi r2, r2, 9 extsh r3, r2 blr GCC produces: _baz: srwi r10,r4,24 insrwi r10,r3,24,0 srawi r9,r3,24 srawi r3,r10,9 extsh r3,r3 blr This implements CodeGen/PowerPC/shl_elim.ll git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36221 91177308-0d34-0410-b5e6-96231b3b80d8
2007-04-17Copy coalescing change to prevent a physical register from being pin to aEvan Cheng
long live interval that has low usage density. 1. Change order of coalescing to join physical registers with virtual registers first before virtual register intervals become too long. 2. Check size and usage density to determine if it's worthwhile to join. 3. If joining is aborted, assign virtual register live interval allocation preference field to the physical register. 4. Register allocator should try to allocate to the preferred register first (if available) to create identify moves that can be eliminated. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36218 91177308-0d34-0410-b5e6-96231b3b80d8
2007-04-17Add a register allocation preference field; add a method to compute size of ↵Evan Cheng
a live interval. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36216 91177308-0d34-0410-b5e6-96231b3b80d8
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