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2009-06-09Add the beginnings of an implementatation of lazy liveness analysis, based ↵Owen Anderson
on "Fast Liveness Checking for SSA-form Programs" by Boissinot, et al. This is still very early, hasn't been tested, and is not yet well documented. More to come soon. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73141 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-07Delete comment and fix typoBruno Cardoso Lopes
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73040 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-07Fix wrong elf class and byte order initializations.Bruno Cardoso Lopes
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73039 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-07Simple ELF32/64 binary files can now be emitted for x86 and x86_64 withoutBruno Cardoso Lopes
relocation sections. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73038 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-07Tweak the expansion code for BIT_CONVERT to generate better code Eli Friedman
converting from an MMX vector to an i64. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73024 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-07Slightly generalize the code that handles shuffles of consecutive loads Eli Friedman
on x86 to handle more cases. Fix a bug in said code that would cause it to read past the end of an object. Rewrite the code in SelectionDAGLegalize::ExpandBUILD_VECTOR to be a bit more general. Remove PerformBuildVectorCombine, which is no longer necessary with these changes. In addition to simplifying the code, with this change, we can now catch a few more cases of consecutive loads. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73012 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-06Fix the expansion for CONCAT_VECTORS so that it doesn't create illegal Eli Friedman
types. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72993 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-06Factor out a couple of helpers.Eli Friedman
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72992 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-06Remove elf specific info from ELFWriter.h to Elf.h. Code cleanup and more ↵Bruno Cardoso Lopes
comments added git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72982 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-06Make SINT_TO_FP/UINT_TO_FP vector legalization queries query on the Eli Friedman
integer type to be consistent with normal operation legalization. No visible change because nothing is actually using this at the moment. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72980 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-05Add new function attribute - noimplicitfloatDevang Patel
Update code generator to use this attribute and remove NoImplicitFloat target option. Update llc to set this attribute when -no-implicit-float command line option is used. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72959 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-05Adapt the x86 build_vector dagcombine to the current state of the legalizer.Nate Begeman
build vectors with i64 elements will only appear on 32b x86 before legalize. Since vector widening occurs during legalize, and produces i64 build_vector elements, the dag combiner is never run on these before legalize splits them into 32b elements. Teach the build_vector dag combine in x86 back end to recognize consecutive loads producing the low part of the vector. Convert the two uses of TLI's consecutive load recognizer to pass LoadSDNodes since that was required implicitly. Add a testcase for the transform. Old: subl $28, %esp movl 32(%esp), %eax movl 4(%eax), %ecx movl %ecx, 4(%esp) movl (%eax), %eax movl %eax, (%esp) movaps (%esp), %xmm0 pmovzxwd %xmm0, %xmm0 movl 36(%esp), %eax movaps %xmm0, (%eax) addl $28, %esp ret New: movl 4(%esp), %eax pmovzxwd (%eax), %xmm0 movl 8(%esp), %eax movaps %xmm0, (%eax) ret git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72957 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-05Remove some unnecessary #includes.Dan Gohman
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72948 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-05Allow libcalls for i16 sdiv/udiv/rem operations.Sanjiv Gupta
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72941 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-05ELF Code Emitter now uses CurBufferPtr, BufferBegin and BufferEnd, as do JIT andBruno Cardoso Lopes
MachO Writer. This will change with the arrival of ObjectCodeEmitter and BinaryObject git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72906 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-04Split the Add, Sub, and Mul instruction opcodes into separateDan Gohman
integer and floating-point opcodes, introducing FAdd, FSub, and FMul. For now, the AsmParser, BitcodeReader, and IRBuilder all preserve backwards compatability, and the Core LLVM APIs preserve backwards compatibility for IR producers. Most front-ends won't need to change immediately. This implements the first step of the plan outlined here: http://nondot.org/sabre/LLVMNotes/IntegerOverflow.txt git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72897 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-04Fix FP_TO_UINT->i32 on ppc32 -mcpu=g5. This wasDale Johannesen
using Promote which won't work because i64 isn't a legal type. It's easy enough to use Custom, but then we have the problem that when the type legalizer is promoting FP_TO_UINT->i16, it has no way of telling it should prefer FP_TO_SINT->i32 to FP_TO_UINT->i32. I have uncomfortably hacked this by making the type legalizer choose FP_TO_SINT when both are Custom. This fixes several regressions in the testsuite. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72891 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-04RALinScan::attemptTrivialCoalescing() was returning a virtual register ↵Evan Cheng
instead of the physical register it is allocated to. This resulted in virtual register(s) being added the live-in sets. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72890 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-04A value defined by an implicit_def can be liven to a use BB. This is ↵Evan Cheng
unfortunate. But register allocator still has to add it to the live-in set of the use BB. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72889 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-04Removed SimpleRewriter.Lang Hames
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72880 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-04Don't do the X * 0.0 -> 0.0 transformation in instcombine, becauseDan Gohman
instcombine doesn't know when it's safe. To partially compensate for this, introduce new code to do this transformation in dagcombine, which can use UnsafeFPMath. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72872 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-04Fix comments.Dan Gohman
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72870 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-04Remove a #include of <iostream>.Dan Gohman
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72828 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-04Removed more testing code that snuck in earlier.Lang Hames
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72825 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-03Move ELFCodeEmiter stuff to new filesBruno Cardoso Lopes
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72785 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-03CMake: Added missing source file to lib/CodeGen/CMakeLists.txt.Oscar Fuentes
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72775 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-03Fix for PR4225: When rewriter reuse a value in a physical register , it ↵Evan Cheng
clear the register kill operand marker and its kill ops information. However, the cleared operand may be a def of a super-register. Clear the kill ops info for the super-register's sub-registers as well. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72758 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-03If there is a def of a super-register followed by a use of a sub-register, ↵Evan Cheng
do *not* add an implicit def of the sub-register. e.g. EAX = ..., AX<imp-def> ... = AX This creates a double-def. Apparently this used to be necessary but is no longer needed. Thanks to Anton for pointing this out. Anton, I cannot create a test case without your uncommitted ARM patches. Please check in a test case for me. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72755 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-03Move structures and classes into header files, providing two new headers andBruno Cardoso Lopes
one new .cpp file, in preparation for merging in the Direct Object Emission changes we're working on. No functional changes. Fixed coding style issues on the original patch. Patch by Aaron Gray git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72754 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-02Fixed warning, removed some temporary validation code that snuck in during ↵Lang Hames
my last commit. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72735 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-02Update to in-place spilling framework. Includes live interval scaling and ↵Lang Hames
trivial rewriter. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72729 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-02Revert 72707 and 72709, for the moment.Dale Johannesen
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72712 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-01Make the implicit inputs and outputs of target-independentDale Johannesen
ADDC/ADDE use MVT::i1 (later, whatever it gets legalized to) instead of MVT::Flag. Remove CARRY_FALSE in favor of 0; adjust all target-independent code to use this format. Most targets will still produce a Flag-setting target-dependent version when selection is done. X86 is converted to use i32 instead, which means TableGen needs to produce different code in xxxGenDAGISel.inc. This keys off the new supportsHasI1 bit in xxxInstrInfo, currently set only for X86; in principle this is temporary and should go away when all other targets have been converted. All relevant X86 instruction patterns are modified to represent setting and using EFLAGS explicitly. The same can be done on other targets. The immediate behavior change is that an ADC/ADD pair are no longer tightly coupled in the X86 scheduler; they can be separated by instructions that don't clobber the flags (MOV). I will soon add some peephole optimizations based on using other instructions that set the flags to feed into ADC. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72707 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-01Accidental commit. This isn't ready for prime time just yet.Bill Wendling
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72699 91177308-0d34-0410-b5e6-96231b3b80d8
2009-05-31Rename CustomLowerResults to CustomLowerNode, sinceDuncan Sands
it is used both when a result is illegal and when an operand is illegal. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72658 91177308-0d34-0410-b5e6-96231b3b80d8
2009-05-30Use uint8_t and int32_t in {JIT,Machine}CodeEmitersBruno Cardoso Lopes
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72650 91177308-0d34-0410-b5e6-96231b3b80d8
2009-05-30First patch in the direction of splitting MachineCodeEmitter in two subclasses:Bruno Cardoso Lopes
JITCodeEmitter and ObjectCodeEmitter. No functional changes yet. Patch by Aaron Gray git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72631 91177308-0d34-0410-b5e6-96231b3b80d8
2009-05-30Untabification.Bill Wendling
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72604 91177308-0d34-0410-b5e6-96231b3b80d8
2009-05-28Do not try to create a MVT type of width 0.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72557 91177308-0d34-0410-b5e6-96231b3b80d8
2009-05-28Re-commit r72514 and r72516 with a fixed version of BR_CC lowering. Eli Friedman
This patch removes some special cases for opcodes and does a bit of cleanup. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72536 91177308-0d34-0410-b5e6-96231b3b80d8
2009-05-28Incorporate patch feedbacks.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72533 91177308-0d34-0410-b5e6-96231b3b80d8
2009-05-28Temporarily revert r72514 (and dependent patch r72516). It was causing thisBill Wendling
failure during llvm-gcc bootstrap: Assertion failed: (!Tmp2.getNode() && "Can't legalize BR_CC with legal condition!"), function ExpandNode, file /Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvmCore.roots/llvmCore~obj/src/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp, line 2923. /Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvmgcc42.roots/llvmgcc42~obj/src/gcc/libgcc2.c:1727: internal compiler error: Abort trap Please submit a full bug report, with preprocessed source if appropriate. See <URL:http://developer.apple.com/bugreporter> for instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72530 91177308-0d34-0410-b5e6-96231b3b80d8
2009-05-28Remove a couple of useless functions.Eli Friedman
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72516 91177308-0d34-0410-b5e6-96231b3b80d8
2009-05-28Remove special cases for more opcodes.Eli Friedman
This is basically the end of this series of patches for LegalizeDAG; the remaining special cases can't be removed without more infrastructure work. There's a FIXME for each relevant opcode near the beginning of SelectionDAGLegalize::LegalizeOp. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72514 91177308-0d34-0410-b5e6-96231b3b80d8
2009-05-28Remove special case for SETCC opcode; add some comments explaining why Eli Friedman
some special cases are necessary. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72511 91177308-0d34-0410-b5e6-96231b3b80d8
2009-05-28Some minor cleanups.Eli Friedman
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72509 91177308-0d34-0410-b5e6-96231b3b80d8
2009-05-28Added optimization that narrow load / op / store and the 'op' is a bit ↵Evan Cheng
twiddling instruction and its second operand is an immediate. If bits that are touched by 'op' can be done with a narrower instruction, reduce the width of the load and store as well. This happens a lot with bitfield manipulation code. e.g. orl $65536, 8(%rax) => orb $1, 10(%rax) Since narrowing is not always a win, e.g. i32 -> i16 is a loss on x86, dag combiner consults with the target before performing the optimization. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72507 91177308-0d34-0410-b5e6-96231b3b80d8
2009-05-27Minor cleanups; add a better explanation for the issue with Eli Friedman
BUILD_VECTOR. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72469 91177308-0d34-0410-b5e6-96231b3b80d8
2009-05-27Remove more special cases for opcodes.Eli Friedman
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72468 91177308-0d34-0410-b5e6-96231b3b80d8
2009-05-27Remove special cases for more opcodes.Eli Friedman
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72467 91177308-0d34-0410-b5e6-96231b3b80d8
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