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2007-04-12the result of an inline asm copy can be an arbitrary VT that the registerChris Lattner
class supports. In the case of vectors, this means we often get the wrong type (e.g. we get v4f32 instead of v8i16). Make sure to convert the vector result to the right type. This fixes CodeGen/X86/2007-04-11-InlineAsmVectorResult.ll git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35944 91177308-0d34-0410-b5e6-96231b3b80d8
2007-04-12fold noop vbitconvert instructionsChris Lattner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35943 91177308-0d34-0410-b5e6-96231b3b80d8
2007-04-12Fix weirdness handling single element vectors.Chris Lattner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35941 91177308-0d34-0410-b5e6-96231b3b80d8
2007-04-12For PR1284:Reid Spencer
Implement the "part_set" intrinsic. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35938 91177308-0d34-0410-b5e6-96231b3b80d8
2007-04-11fix an infinite loop compiling ldecod, notice by JeffC.Chris Lattner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35910 91177308-0d34-0410-b5e6-96231b3b80d8
2007-04-11Fix this harder.Chris Lattner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35888 91177308-0d34-0410-b5e6-96231b3b80d8
2007-04-11don't create shifts by zero, fix some problems with my previous patchChris Lattner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35887 91177308-0d34-0410-b5e6-96231b3b80d8
2007-04-11Teach the codegen to turn [aez]ext (setcc) -> selectcc of 1/0, which oftenChris Lattner
allows other simplifications. For example, this compiles: int isnegative(unsigned int X) { return !(X < 2147483648U); } Into this code: x86: movl 4(%esp), %eax shrl $31, %eax ret arm: mov r0, r0, lsr #31 bx lr thumb: lsr r0, r0, #31 bx lr instead of: x86: cmpl $0, 4(%esp) sets %al movzbl %al, %eax ret arm: mov r3, #0 cmp r0, #0 movlt r3, #1 mov r0, r3 bx lr thumb: mov r2, #1 mov r1, #0 cmp r0, #0 blt LBB1_2 @entry LBB1_1: @entry cpy r2, r1 LBB1_2: @entry cpy r0, r2 bx lr Testcase here: test/CodeGen/Generic/ispositive.ll git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35883 91177308-0d34-0410-b5e6-96231b3b80d8
2007-04-11Codegen integer abs more efficiently using the trick from the PPC CWG. ThisChris Lattner
improves codegen on many architectures. Tests committed as CodeGen/*/iabs.ll X86 Old: X86 New: _test: _test: movl 4(%esp), %ecx movl 4(%esp), %eax movl %ecx, %eax movl %eax, %ecx negl %eax sarl $31, %ecx testl %ecx, %ecx addl %ecx, %eax cmovns %ecx, %eax xorl %ecx, %eax ret ret PPC Old: PPC New: _test: _test: cmpwi cr0, r3, -1 srawi r2, r3, 31 neg r2, r3 add r3, r3, r2 bgt cr0, LBB1_2 ; xor r3, r3, r2 LBB1_1: ; blr mr r3, r2 LBB1_2: ; blr ARM Old: ARM New: _test: _test: rsb r3, r0, #0 add r3, r0, r0, asr #31 cmp r0, #0 eor r0, r3, r0, asr #31 movge r3, r0 bx lr mov r0, r3 bx lr Thumb Old: Thumb New: _test: _test: neg r2, r0 asr r2, r0, #31 cmp r0, #0 add r0, r0, r2 bge LBB1_2 eor r0, r2 LBB1_1: @ bx lr cpy r0, r2 LBB1_2: @ bx lr Sparc Old: Sparc New: test: test: save -96, %o6, %o6 save -96, %o6, %o6 sethi 0, %l0 sra %i0, 31, %l0 sub %l0, %i0, %l0 add %i0, %l0, %l1 subcc %i0, -1, %l1 xor %l1, %l0, %i0 bg .BB1_2 restore %g0, %g0, %g0 nop retl .BB1_1: nop or %g0, %l0, %i0 .BB1_2: restore %g0, %g0, %g0 retl nop It also helps alpha/ia64 :) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35881 91177308-0d34-0410-b5e6-96231b3b80d8
2007-04-11For PR1146:Reid Spencer
Put the parameter attributes in their own ParamAttr name space. Adjust the rest of llvm as a result. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35877 91177308-0d34-0410-b5e6-96231b3b80d8
2007-04-10apparently some people commit without building the tree, or they forget toChris Lattner
commit a LOT of files. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35858 91177308-0d34-0410-b5e6-96231b3b80d8
2007-04-09No longer needed.Jeff Cohen
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35850 91177308-0d34-0410-b5e6-96231b3b80d8
2007-04-09remove dead target hooks.Chris Lattner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35847 91177308-0d34-0410-b5e6-96231b3b80d8
2007-04-09remove some dead target hooks, subsumed by isLegalAddressingModeChris Lattner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35840 91177308-0d34-0410-b5e6-96231b3b80d8
2007-04-09Use integer log for metric calculationAnton Korobeynikov
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35834 91177308-0d34-0410-b5e6-96231b3b80d8
2007-04-09Unbreak VC++ build.Jeff Cohen
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35817 91177308-0d34-0410-b5e6-96231b3b80d8
2007-04-09Next stage into switch lowering refactoringAnton Korobeynikov
1. Fix some bugs in the jump table lowering threshold 2. Implement much better metric for optimal pivot selection 3. Tune thresholds for different lowering methods 4. Implement shift-and trick for lowering small (<machine word length) cases with few destinations. Good testcase will follow. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35816 91177308-0d34-0410-b5e6-96231b3b80d8
2007-04-09For PR1146:Reid Spencer
Adapt handling of parameter attributes to use the new ParamAttrsList class. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35814 91177308-0d34-0410-b5e6-96231b3b80d8
2007-04-09implement CodeGen/X86/inline-asm-x-scalar.ll:test3Chris Lattner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35802 91177308-0d34-0410-b5e6-96231b3b80d8
2007-04-09add some assertionsChris Lattner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35800 91177308-0d34-0410-b5e6-96231b3b80d8
2007-04-09Fix a bug introduced with my previous patch, where it didn't correctly handleChris Lattner
instructions which replace themselves when FI's are rewritten (common on ppc). This fixes CodeGen/PowerPC/2006-10-17-ppc64-alloca.ll git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35789 91177308-0d34-0410-b5e6-96231b3b80d8
2007-04-09Fix CodeGen/Generic/2007-04-08-MultipleFrameIndices.ll and PR1308:Chris Lattner
some instructions can have multiple frame indices in them. If this happens, rewrite all of them. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35785 91177308-0d34-0410-b5e6-96231b3b80d8
2007-04-09Fix PR1316Chris Lattner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35783 91177308-0d34-0410-b5e6-96231b3b80d8
2007-04-08Fix for CodeGen/X86/2007-04-08-InlineAsmCrash.ll and PR1314Chris Lattner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35779 91177308-0d34-0410-b5e6-96231b3b80d8
2007-04-06minor comment fixChris Lattner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35696 91177308-0d34-0410-b5e6-96231b3b80d8
2007-04-05Change the bit_part_select (non)implementation from "return 0" to abort.Reid Spencer
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35679 91177308-0d34-0410-b5e6-96231b3b80d8
2007-04-04Implement the llvm.bit.part_select.iN.iN.iN overloaded intrinsic.Reid Spencer
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35678 91177308-0d34-0410-b5e6-96231b3b80d8
2007-04-04Properly emit range comparisons for switch cases, where neighbour casesAnton Korobeynikov
go to the same destination. Now we're producing really good code for switch-lower-feature.ll testcase git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35672 91177308-0d34-0410-b5e6-96231b3b80d8
2007-04-04Re-materialize all loads from fixed stack slots.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35660 91177308-0d34-0410-b5e6-96231b3b80d8
2007-04-04Trivially re-materializable instructions have spill weights that are half of ↵Evan Cheng
what it would be otherwise. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35658 91177308-0d34-0410-b5e6-96231b3b80d8
2007-04-03Bad bad bug. findRegisterUseOperand() returns -1 if a use if not found.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35618 91177308-0d34-0410-b5e6-96231b3b80d8
2007-04-021. Insert custom lowering hooks for ISD::ROTR and ISD::ROTL.Scott Michel
2. Help DAGCombiner recognize zero/sign/any-extended versions of ROTR and ROTL patterns. This was motivated by the X86/rotate.ll testcase, which should now generate code for other platforms (and soon-to-come platforms.) Rewrote code slightly to make it easier to read. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35605 91177308-0d34-0410-b5e6-96231b3b80d8
2007-04-02Ugh. Copy coalescer does not update register numbers.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35600 91177308-0d34-0410-b5e6-96231b3b80d8
2007-04-02For PR1297:Reid Spencer
Make sure that the CTPOP result is casted to i32 as the bit counting intrinsics all return i32 now (this affects CTLZ and CTTZ as well). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35567 91177308-0d34-0410-b5e6-96231b3b80d8
2007-04-01For PR1297:Reid Spencer
Support overloaded intrinsics bswap, ctpop, cttz, ctlz. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35547 91177308-0d34-0410-b5e6-96231b3b80d8
2007-04-01For PR1297:Reid Spencer
Adjust for changes in the bit counting intrinsics. They all return i32 now so we have to trunc/zext the DAG node accordingly. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35546 91177308-0d34-0410-b5e6-96231b3b80d8
2007-04-01For PR1297:Reid Spencer
Change getOperationName to return std::string instead of const char* git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35545 91177308-0d34-0410-b5e6-96231b3b80d8
2007-03-31move a bunch of code out of the sdisel pass into its own opt pass ↵Chris Lattner
"codegenprepare". git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35529 91177308-0d34-0410-b5e6-96231b3b80d8
2007-03-31switch TL::getValueType to use MVT::getValueType.Chris Lattner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35527 91177308-0d34-0410-b5e6-96231b3b80d8
2007-03-31Add a -print-lsr-output option to LLC, to print the output of the LSR pass.Chris Lattner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35522 91177308-0d34-0410-b5e6-96231b3b80d8
2007-03-30add one addressing mode description hook to rule them all.Chris Lattner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35520 91177308-0d34-0410-b5e6-96231b3b80d8
2007-03-30Fix incorrect combination of different loads. Reenable zext-over-truncateDale Johannesen
combination. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35517 91177308-0d34-0410-b5e6-96231b3b80d8
2007-03-30Don't add the same MI to register reuse "last def/use" twice if it reads theEvan Cheng
register more than once. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35513 91177308-0d34-0410-b5e6-96231b3b80d8
2007-03-30Bug fix for PR1279. When isDead is propagate by copy coalescing, we keep lengthEvan Cheng
of dead def live interval at 1 to avoid multiple def's targeting the same register. The previous patch missed a case where the source operand is live-in. In that case, remove the whole interval. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35512 91177308-0d34-0410-b5e6-96231b3b80d8
2007-03-29Disable load width reduction xform of variant (zext (truncate load x)) forEvan Cheng
big endian targets until llvm-gcc build issue has been resolved. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35449 91177308-0d34-0410-b5e6-96231b3b80d8
2007-03-29New entries.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35445 91177308-0d34-0410-b5e6-96231b3b80d8
2007-03-28Notes on re-materialization.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35420 91177308-0d34-0410-b5e6-96231b3b80d8
2007-03-28Move rematerialization out of beta.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35419 91177308-0d34-0410-b5e6-96231b3b80d8
2007-03-28Scale 1 is always ok.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35407 91177308-0d34-0410-b5e6-96231b3b80d8
2007-03-28Remove isLegalAddressImmediate.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35406 91177308-0d34-0410-b5e6-96231b3b80d8
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