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2010-07-13Add an assertion to make PR7542 fail consistently.Jakob Stoklund Olesen
LiveInterval::overlapsFrom dereferences end() if it is called on an empty interval. It would be reasonable to just return false - an empty interval doesn't overlap anything, but I want to know who is doing it first. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108264 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-13Fix LiveInterval::overlaps so it doesn't claim touching intervals overlap.Jakob Stoklund Olesen
Also, one binary search is enough. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108261 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-13Don't add memory operands to storeRegToStackSlot / loadRegFromStackSlot results,Jakob Stoklund Olesen
they already have one. This fixes the himenobmtxpa miscompilation on ARM. The PostRA scheduler got confused by the double memoperand and hoisted a stack slot load above a store to the same slot. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108219 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-12Fix a typo and fit in 80 columns. Found by Bob Wilson.Rafael Espindola
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108164 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-12Convert some tab stops into spaces.Duncan Sands
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108130 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-12Convert the last use of getPhysicalRegisterRegClass and remove it.Rafael Espindola
AggressiveAntiDepBreaker should not be using getPhysicalRegisterRegClass. An instruction might be using a register that can only be replaced with one from a subclass of getPhysicalRegisterRegClass. With this patch we use getMinimalPhysRegClass. This is correct, but conservative. We should check the uses of the register and select the largest register class that can be used in all of them. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108122 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-12Don't use getPhysicalRegisterRegClass in PBQP. The existing checks that theRafael Espindola
physical register can be allocated in the class of the virtual are sufficient. I think that the test for virtual registers is more strict than it needs to be, it should be possible to coalesce two virtual registers the class of one is a subclass of the other. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108118 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-12Convert the last getPhysicalRegisterRegClass in VirtRegRewriter.cpp toRafael Espindola
getMinimalPhysRegClass. It was used to produce spills, and it is better to use the most specific class if possible. Update getLoadStoreRegOpcode to handle GR32_AD. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108115 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-12change machinelicm to use MachineInstr::isSafeToMove. NoChris Lattner
intended functionality change. The avoidance of hoistiing implicitdef seems wrong though. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108109 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-11Remove TargetInstrInfo::copyRegToReg entirely.Jakob Stoklund Olesen
Targets must now implement TargetInstrInfo::copyPhysReg instead. There is no longer a default implementation forwarding to copyRegToReg. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108095 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-11Convert uses of getPhysicalRegisterRegClass in VirtRegRewriter.cpp.Rafael Espindola
The first one was used just to call isSafeToMoveRegClassDefs. In general, using a more specific reg class is better, in practice only x86 implements that method and the results are always the same. The second one is in FindFreeRegister and is used to check if a register is in a register class, a much more direct call to contains is better as it should cover more cases and is faster. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108093 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-11Remove two other uses of ATTRIBUTE_UNUSED for variables only used withinChandler Carruth
assert()s, switching to void-casts. Removed an unneeded Compiler.h include as a result. There are two other uses in LLVM, but they're not due to assert()s, so I've left them alone. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108088 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-11Use COPY for fast-isel bitconvert, but don't create cross-class copies.Jakob Stoklund Olesen
This doesn't change the behavior of SelectBitcast for X86. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108073 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-11Fix va_arg for doubles. With this patch VAARG nodes always contain theRafael Espindola
correct alignment information, which simplifies ExpandRes_VAARG a bit. The patch introduces a new alignment information to TargetLoweringInfo. This is needed since the two natural candidates cannot be used: * The 's' in target data: If this is set to the minimal alignment of any argument, getCallFrameTypeAlignment would return 4 for doubles on ARM for example. * The getTransientStackAlignment method. It is possible for an architecture to have argument less aligned than what we maintain the stack pointer. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108072 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-11Use COPY for extracting ImplicitDef'ed values from fast-isel instructions.Jakob Stoklund Olesen
This assumes that the registers can be copied which is probably a safe assumption. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108070 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-11Use COPY in FastISel everywhere it is safe and trivial.Jakob Stoklund Olesen
The remaining copyRegToReg calls actually check the return value (shock!), so we cannot trivially replace them with COPY instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108069 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-10Replace copyRegToReg with COPY everywhere in lib/CodeGen except for FastISel.Jakob Stoklund Olesen
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108062 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-10Only collect subreg extracting copies for later coalescing.Jakob Stoklund Olesen
This also avoids fatal copies from physregs. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108061 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-10Fix a bug in the code which re-inserts DBG_VALUE nodes after scheduling;Dan Gohman
if a block is split (by a custom inserter), the insert point may be in a different block than it was originally. This fixes 32-bit llvm-gcc bootstrap builds, and I haven't been able to reproduce it otherwise. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108060 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-10Emit COPY instructions instead of using copyRegToReg in InstrEmitter,Jakob Stoklund Olesen
ScheduleDAGEmit, TwoAddressLowering, and PHIElimination. This switches the bulk of register copies to using COPY, but many less used copyRegToReg calls remain. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108050 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-10Insert IMPLICIT_DEF instructions at the current insert position, notDan Gohman
at the end of the block. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108045 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-10Reapply bottom-up fast-isel, with several fixes for x86-32:Dan Gohman
- Check getBytesToPopOnReturn(). - Eschew ST0 and ST1 for return values. - Fix the PIC base register initialization so that it doesn't ever fail to end up the top of the entry block. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108039 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-09Update DBG_VALUE to refer appropriate stack slot in case of a spill.Devang Patel
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108023 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-09Fix small bug in isMoveInstr -> COPY translationJakob Stoklund Olesen
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108013 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-09Automatically fold COPY instructions into stack load/store.Jakob Stoklund Olesen
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108012 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-09Remat uncoalescable COPY instrsJakob Stoklund Olesen
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108010 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-09Clarify what mysterious check means.Bill Wendling
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108005 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-09Fix MachineLICM to actually visit inner loops.Dan Gohman
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108001 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-09Change TII::foldMemoryOperand API to require the machine instruction to beJakob Stoklund Olesen
inserted in a MBB, and return an already inserted MI. This target API change is necessary to allow foldMemoryOperand to call storeToStackSlot and loadFromStackSlot when folding a COPY to a stack slot reference in a target independent way. The foldMemoryOperandImpl hook is going to change in the same way, but I'll wait until COPY folding is actually implemented. Most targets only fold copies and won't need to specialize this hook at all. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107991 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-09--- Reverse-merging r107947 into '.':Bob Wilson
U utils/TableGen/FastISelEmitter.cpp --- Reverse-merging r107943 into '.': U test/CodeGen/X86/fast-isel.ll U test/CodeGen/X86/fast-isel-loads.ll U include/llvm/Target/TargetLowering.h U include/llvm/Support/PassNameParser.h U include/llvm/CodeGen/FunctionLoweringInfo.h U include/llvm/CodeGen/CallingConvLower.h U include/llvm/CodeGen/FastISel.h U include/llvm/CodeGen/SelectionDAGISel.h U lib/CodeGen/LLVMTargetMachine.cpp U lib/CodeGen/CallingConvLower.cpp U lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp U lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp U lib/CodeGen/SelectionDAG/FastISel.cpp U lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp U lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp U lib/CodeGen/SelectionDAG/InstrEmitter.cpp U lib/CodeGen/SelectionDAG/TargetLowering.cpp U lib/Target/XCore/XCoreISelLowering.cpp U lib/Target/XCore/XCoreISelLowering.h U lib/Target/X86/X86ISelLowering.cpp U lib/Target/X86/X86FastISel.cpp U lib/Target/X86/X86ISelLowering.h git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107987 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-09cache result of operator*Gabor Greif
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107980 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-09Avoid creating %physreg:subidx operands in ↵Jakob Stoklund Olesen
SimpleRegisterCoalescing::RemoveCopyByCommutingDef. This fixes PR7602. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107957 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-09Deal with a few remaining spots that assume physical registers have live ↵Jakob Stoklund Olesen
intervals. This fixes PR7601. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107955 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-09Fix broken isCopy handling in TrimLiveIntervalToLastUse.Jakob Stoklund Olesen
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107950 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-09Handle COPY in VirtRegRewriter.Jakob Stoklund Olesen
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107949 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-09Re-apply bottom-up fast-isel, with fixes. Be very careful to avoid emittingDan Gohman
a DBG_VALUE after a terminator, or emitting any instructions before an EH_LABEL. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107943 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-09Reenable DAG combining for vector shuffles. It looks like it was temporarilyBob Wilson
disabled and then never turned back on again. Adjust some tests, one because this change avoids an unnecessary instruction, and the other to make it continue testing what it was intended to test. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107941 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-08Reverting r107918 and r107919. Radar 8063111.Stuart Hastings
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107930 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-08Revert "Fix broken isCopy handling in TrimLiveIntervalToLastUse"Jakob Stoklund Olesen
This reverts commit 107921. It broke the clang self host. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107926 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-08Relax assertion. In optimized code, it is possible that first instruction is ↵Devang Patel
coming from a inlined function. This fixes PR7596 . git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107923 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-08Extension of r107506. Make sure that we don't mark a function as having a callBill Wendling
if the inline ASM doesn't need a stack frame. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107922 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-08Fix broken isCopy handling in TrimLiveIntervalToLastUseJakob Stoklund Olesen
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107921 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-08Fix decl/def debug info for template functions. Radar 8063111.Stuart Hastings
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107919 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-08Reuse DIEInteger for 1. This is frequently used while emitting an attribute ↵Devang Patel
using dwarf::DW_FORM_flag form. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107903 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-08Clean up scavengeRegister() a bit to prefer available regs, which allowsJim Grosbach
the simplification of frame index register scavenging to not have to check for available registers directly and instead just let scavengeRegister() handle it. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107880 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-08Convert EXTRACT_SUBREG to COPY when emitting machine instrs.Jakob Stoklund Olesen
EXTRACT_SUBREG no longer appears as a machine instruction. Use COPY instead. Add isCopy() checks in many places using isMoveInstr() and isExtractSubreg(). The isMoveInstr hook will be removed later. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107879 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-08Remove references to INSERT_SUBREG after de-SSA.Jakob Stoklund Olesen
Fix X86InstrInfo::convertToThreeAddressWithLEA to generate COPY instead of INSERT_SUBREG. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107878 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-08Merge the duplicated iabs optimization in DAGCombiner and let it detected a ↵Benjamin Kramer
few more idioms. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107868 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-08Add TargetInstrInfo::copyPhysReg hook and use it from LowerSubregs.Jakob Stoklund Olesen
This target hook is intended to replace copyRegToReg entirely, but for now it calls copyRegToReg. Any remaining calls to copyRegToReg wil be replaced by COPY instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107854 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-08Revert 107840 107839 107813 107804 107800 107797 107791.Dan Gohman
Debug info intrinsics win for now. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107850 91177308-0d34-0410-b5e6-96231b3b80d8
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