aboutsummaryrefslogtreecommitdiff
path: root/lib/CodeGen
AgeCommit message (Collapse)Author
2011-06-08Fix count.Rafael Espindola
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132749 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-08Count how many phis we are creating.Rafael Espindola
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132748 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-07Fix an issue where the two-address conversion pass incorrectly rewrites untiedCameron Zwarich
operands to an early clobber register. This fixes <rdar://problem/9566076>. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132738 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-07Fix a silly error I introduce in r131951.Rafael Espindola
Fixes PR10095. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132735 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-07Fix a merge bug in preRAsched for handling physreg aliases.Andrew Trick
I've been sitting on this long enough trying to find a test case. I think the fix should go in now, but I'll keep working on the test case. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132701 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-06Simplify local live range splitting's safeguard to fix PR10070.Jakob Stoklund Olesen
When local live range splitting creates a live range with the same number of instructions as the old range, mark it as RS_Local. When such a range is seen again, require that it be split in a way that reduces the number of instructions. That guarantees we are making progress while still being able to perform 3 -> 2+3 splits as required by PR10070. This also means that the PrevSlot map is no longer needed. This was also used to estimate new spill weights, but that is no longer necessary after slotIndexes::insertMachineInstrInMaps() got the extra Late insertion argument. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132697 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-06Get allocation orders from RegisterClassInfo when possible.Jakob Stoklund Olesen
Only target-dependent hints require callbacks. The RCI allocation order has CSR aliases last according to their order of appearance in the getCalleeSavedRegs list. This can depend on the calling convention. This way, AllocationOrder::next doesn't have to check for reserved registers, and CSRs are always allocated last, even with weird calling conventions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132690 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-06Add methods to support the integer-promotion of vector types. Methods toNadav Rotem
legalize SDNodes such as BUILD_VECTOR, EXTRACT_VECTOR_ELT, etc. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132689 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-06Avoid FGETSIGN of 80-bit types. Fixes PR10085.Stuart Hastings
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132681 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-06Don't try to be clever, just preserve the target's allocation order.Jakob Stoklund Olesen
The order of registers returned by getCalleeSavedRegs is used to lay out the fixed stack slots for CSRs. Some targets like their CSRs used from one end, and some targets want them used from the other end. When computing an allocation order, simply preserve the relative ordering of CSRs that the target specifies in its allocation order. Reordering CSRs would break some targets, ARM in particular. We still place volatiles before the CSRs, providing slightly better results with different calling conventions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132680 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-06PR10077: fix fast-isel of extractvalue of aggregate constants.Eli Friedman
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132676 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-05Use path API for path concatenation.Benjamin Kramer
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132668 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-04TypeLegalizer: Add support for passing of vector-promoted types in registers ↵Nadav Rotem
(copyFromParts/copyToParts). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132649 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-04TypeLegalizer: Fix a bug in the promotion of elements of integer vectors.Nadav Rotem
(only happens when using the -promote-elements option). The correct legalization order is to first try to promote element. Next, we try to widen vectors. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132648 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-03Switch AllocationOrder to using RegisterClassInfo instead of a BitVectorJakob Stoklund Olesen
of reserved registers. Use RegisterClassInfo in RABasic as well. This slightly changes som allocation orders because RegisterClassInfo puts CSR aliases last. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132581 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-03Preserve the original ordering when a CSR has multiple aliases.Jakob Stoklund Olesen
Previously, these aliases would be ordered alphabetically. (BH, BL) Print out the computed allocation orders. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132580 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-03Add a TODO about memory operands.Eric Christopher
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132559 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-02Avoid calling TRI->getAllocatableSet in RAFast.Jakob Stoklund Olesen
When compiling a program with lots of small functions like 483.xalancbmk, this makes RAFast 11% faster. Add some comments to clarify the difference between unallocatable and reserved registers. It's quite subtle. The fast register allocator depends on EFLAGS' not being allocatable on x86. That way it can completely avoid tracking liveness, and it won't mind when there are multiple uses of a single def. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132514 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-02Have LowerOperandForConstraint handle multiple character constraints.Eric Christopher
Part of rdar://9119939 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132510 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-02Make it possible to have unallocatable register classes.Jakob Stoklund Olesen
Some register classes are only used for instruction operand constraints. They should never be used for virtual registers. Previously, those register classes were given an empty allocation order, but now you can say 'let isAllocatable=0' in the register class definition. TableGen calculates if a register is part of any allocatable register class, and makes that information available in TargetRegisterDesc::inAllocatableClass. The goal here is to eliminate use cases for overriding allocation_order_* methods. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132508 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-02Just use a SmallVector.Jakob Stoklund Olesen
I was confused whether new uint8_t[] would zero-initialize the returned array, and it seems that so is gcc-4.0. This should fix the test failures on darwin 9. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132500 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-02Remove dead code.Devang Patel
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132488 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-02Update DBG_VALUEs while breaking anti dependencies.Devang Patel
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132487 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-02During post RA scheduling, do not try to chase reg defs. to preserve ↵Devang Patel
DBG_VALUEs. This approach has several downsides, for example, it does not work when dbg value is a constant integer, it does not work if reg is defined more than once, it places end of debug value range markers in the wrong place. It even causes misleading incorrect debug info when duplicate DBG_VALUE instructions point to same reg def. Instead, use simpler approach and let DBG_VALUE follow its predecessor instruction. After live debug value analysis pass, all DBG_VALUE instruction are placed at the right place. Thanks Jakob for the hint! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132483 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-02Revert 132424 to fix PR10068.Rafael Espindola
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132479 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-02Use RegisterClassInfo::getOrder in RAFast.Jakob Stoklund Olesen
This saves two virtual function calls and an Allocatable BitVector test, making RAFast run 2% faster. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132471 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-02Start with a zeroed CSRNum map.Benjamin Kramer
Found by valgrind. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132457 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-02Initialize members to fix problem found by valgrind.Jakob Stoklund Olesen
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132456 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-02Use TRI::has{Sub,Super}ClassEq() where possible.Jakob Stoklund Olesen
No functional change. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132455 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-02Add a RegisterClassInfo class that lazily caches information aboutJakob Stoklund Olesen
register classes. It provides information for each register class that cannot be determined statically, like: - The number of allocatable registers in a class after filtering out the reserved and invalid registers. - The preferred allocation order with registers that overlap callee-saved registers last. - The last callee-saved register that overlaps a given physical register. This information usually doesn't change between functions, so it is reused for compiling multiple functions when possible. The many possible combinations of reserved and callee saves registers makes it unfeasible to compute this information statically in TableGen. Use RegisterClassInfo to count available registers in various heuristics in SimpleRegisterCoalescing, making the pass run 4% faster. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132450 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-01A DBG_VALUE that truncates a range does not start another dbg value range.Devang Patel
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132433 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-01Do not drop constant values when a variable's content is described using ↵Devang Patel
.debug_loc entries. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132427 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-01Recommit 132404 with fixes. rdar://problem/5993888Stuart Hastings
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132424 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-01Allow bitcasts between valid types of the same size and vectorEric Christopher
types if the vector type is legal. Fixes rdar://9306086 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132420 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-01Refactor LegalizeTypes: Erase LegalizeAction and make the type legalizer useNadav Rotem
the TargetLowering enum. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132418 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-01Revert r132358 "Simplify the eviction policy by making the failsafe explicit."Jakob Stoklund Olesen
This commit caused regressions in i386 flops-[568], matrix, salsa20, 256.bzip2, and enc-md5. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132413 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-01Fix double FGETSIGN to work on x86_32; followup to 132396.Stuart Hastings
rdar://problem/5660695 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132411 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-01Turn on FGETSIGN for x86. Followup to 132388. rdar://problem/5660695Stuart Hastings
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132396 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-01This patch is another step in the direction of adding vector select. In thisNadav Rotem
patch we add a flag to enable a new type legalization decision - to promote integer elements in vectors. Currently, the rest of the codegen does not support this kind of legalization. This flag will be removed when the transition is complete. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132394 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-01Add an issue width check to the postRA scheduler. Patch by Max Kazakov!Andrew Trick
For targets with no itinerary (x86) it is a nop by default. For targets with issue width already expressed in the itinerary (ARM) it bypasses a scoreboard check but otherwise does not affect the schedule. It does make the code more consistent and complete and allows new targets to specify their issue width in an arbitrary way. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132385 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-01The ARM stuff already calls the Resume function, not the Resume_or_Rethrow. ItBill Wendling
turns out that it could cause an infinite loop in some situations. If this code is triggered and it converts a cleanup into a catchall, but that cleanup was in already in a cleanup, then the _Unwind_SjLj_Resume could infinite loop. I.e., the code doesn't consume the exception object and passes it on to _Unwind_SjLj_Resume. But _USjLjR expects it to be consumed (since it's landing at a catchall instead of a cleanup). So it uses the values that are presently there, which are the values that tell it to jump to the fake landing pad. <rdar://problem/9508402> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132381 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-01Incomplete type may not have corresponding DIE, so do not check DIEEntry ↵Devang Patel
eagerly. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132377 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-31Refactor.Devang Patel
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132373 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-31Include global types, that are referenced through local variables, in ↵Devang Patel
debug_pubtypes list. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132371 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-31Simplify the eviction policy by making the failsafe explicit.Jakob Stoklund Olesen
When assigned ranges are evicted, they are put in the RS_Evicted stage and are not allowed to evict anything else. That prevents looping automatically. When evicting ranges just to get a cheaper register, use only spill weights to find the possible candidates. Avoid breaking hints for this purpose, it is not worth it. Start implementing more complex eviction heuristics, guarded by the temporary -complex-eviction flag. The initial version permits a heavier range to be evicted if it doesn't have any uses where the evicting range is live. This makes it a good candidate for live ranfge splitting. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132358 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-30Reapply r132245 with a fix for the bug that broke the darwin9/i386 build.Jakob Stoklund Olesen
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132309 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-30Emit the handler's data area. For GCC-style exceptions under Win64, theCharles Davis
handler's data area starts with a 4-byte reference to the personality function, followed by the DWARF LSDA. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132302 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-29Revert r132245, "Create two BlockInfo entries when a live range is ↵Jakob Stoklund Olesen
discontinuous through a block." This commit seems to have broken a darwin 9 tester. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132299 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-29Fix PR10046 by updating LiveVariables kill info when splitting live ranges.Jakob Stoklund Olesen
This only affects targets like Mips where branch instructions may kill virtual registers. Most other targets branch on flag values, so virtual registers are not involved. The problem is that MachineBasicBlock::updateTerminator deletes branches and inserts new ones while LiveVariables keeps a list of pointers to instructions that kill virtual registers. That list wasn't properly updated in MBB::SplitCriticalEdge. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132298 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-29When generating against the Win64 EH scheme, set the handler to the GCC-specificCharles Davis
handler. At this moment, only GCC-style exceptions are supported. Other kinds of exceptions, including "traditional" SEH and Microsoft Visual C++ exceptions, need more work--and an compiler exception model that isn't specific to GCC-style exceptions! In particular, I imagine that it would be possible to mix "traditional" SEH with GCC-style EH or Microsoft C++ EH. Currently LLVM has no way (beyond some target-specific defaults and whole-module compiler switches) of knowing which scheme to use when. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132283 91177308-0d34-0410-b5e6-96231b3b80d8
generated by cgit v1.2.3-18-g5258 (git 2.32.0) at 2025-07-16 23:51:37 +0000