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2011-08-08Hoist hasLoadFromStackSlot and hasStoreToStackSlot.Jakob Stoklund Olesen
These the methods are target-independent since they simply scan the memory operands. They can live in TargetInstrInfoImpl. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137063 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-08Simplify by creating parent first.Devang Patel
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137056 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-06Fix typo. Thanks, Andy!Jakob Stoklund Olesen
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137023 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-05Reject RS_Spill ranges from local splitting as well.Jakob Stoklund Olesen
All new local ranges are marked as RS_New now, so there is no need to attempt splitting of RS_Spill ranges any more. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137002 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-05Only mark remainder intervals as RS_Spill after per-block splitting.Jakob Stoklund Olesen
The local ranges created get to stay in the RS_New stage, just like for local and region splitting. This gives tryLocalSplit a bit more freedom the first time it sees one of these new local ranges. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137001 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-05Remember to update LiveDebugVariables after per-block splitting.Jakob Stoklund Olesen
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136996 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-05Extract per-block splitting into its own method.Jakob Stoklund Olesen
No functional change. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136994 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-05Delete getMultiUseBlocks and splitSingleBlocks.Jakob Stoklund Olesen
These functions are no longer used, and they are easily replaced with a loop calling shouldSplitSingleBlock and splitSingleBlock. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136993 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-05Also use shouldSplitSingleBlock() in the fallback splitting mode.Jakob Stoklund Olesen
Drop the use of SplitAnalysis::getMultiUseBlocks, there is no need to go through a SmallPtrSet any more. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136992 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-05Split around single instructions to enable register class inflation.Jakob Stoklund Olesen
Normally, we don't create a live range for a single instruction in a basic block, the spiller does that anyway. However, when splitting a live range that belongs to a proper register sub-class, inserting these extra COPY instructions completely remove the constraints from the remainder interval, and it may be allocated from the larger super-class. The spiller will mop up these small live ranges if we end up spilling anyway. It calls them snippets. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136989 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-05Detect proper register sub-classes.Jakob Stoklund Olesen
Some instructions require restricted register classes, but most of the time that doesn't affect register allocation. For example, some instructions don't work with the stack pointer, but that is a reserved register anyway. Sometimes it matters, GR32_ABCD only has 4 allocatable registers. For such a proper sub-class, the register allocator should try to enable register class inflation since that makes more registers available for allocation. Make sure only legal super-classes are considered. For example, tGPR is not a proper sub-class in Thumb mode, but in ARM mode it is. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136981 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-05Fix liveness computations in BranchFolding.Jakob Stoklund Olesen
The old code would look at kills and defs in one pass over the instruction operands, causing problems with this code: %R0<def>, %CPSR<def,dead> = tLSLri %R5<kill>, 2, pred:14, pred:%noreg %R0<def>, %CPSR<def,dead> = tADDrr %R4<kill>, %R0<kill>, pred:14, %pred:%noreg The last instruction kills and redefines %R0, so it is still live after the instruction. This caused a register scavenger crash when compiling 483.xalancbmk for armv6. I am not including a test case because it requires too much bad luck to expose this old bug. First you need to convince the register allocator to use %R0 twice on the tADDrr instruction, then you have to convince BranchFolding to do something that causes it to run the register scavenger on he bad block. <rdar://problem/9898200> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136973 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-05Temporarily revert r135528 which distinguishes between two copies of oneChandler Carruth
inlined variable, based on the discussion in PR10542. This explodes the runtime of several passes down the pipeline due to a large number of "copies" remaining live across a large function. This only shows up with both debug and opt, but when it does it creates a many-minute compile when self-hosting LLVM+Clang. There are several other cases that show these types of regressions. All of this is tracked in PR10542, and progress is being made on fixing the issue. Once its addressed, the re-instated, but until then this restores the performance for self-hosting and other opt+debug builds. Devang, let me know if this causes any trouble, or impedes fixing it in any way, and thanks for working on this! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136953 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-04Count the total amount of stack space used in compiled functions.Jakob Stoklund Olesen
Patch by Ivan Krasin! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136921 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-04Print DBG_VALUE variable's location info as a comment.Devang Patel
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136916 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-04Increment counter inside insertDebugValue().Devang Patel
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136915 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-04Add counter.Devang Patel
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136901 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-03Correctly handle multiple DBG_VALUE instructions at the same SlotIndex.Jakob Stoklund Olesen
It is possible to have multiple DBG_VALUEs for the same variable: 32L TEST32rr %vreg0<kill>, %vreg0, %EFLAGS<imp-def>; GR32:%vreg0 DBG_VALUE 2, 0, !"i" DBG_VALUE %noreg, %0, !"i" When that happens, keep the last one instead of the first. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136842 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-03Enable compact region splitting by default.Jakob Stoklund Olesen
This helps generate better code in functions with high register pressure. The previous version of compact region splitting caused regressions because the regions were a bit too large. A stronger negative bias applied in r136832 fixed this problem. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136836 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-03Do not drop undef debug values. These are used as range termination marker ↵Devang Patel
by live debug variable pass. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136834 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-03Be more conservative when forming compact regions.Jakob Stoklund Olesen
Apply twice the negative bias on transparent blocks when computing the compact regions. This excludes loop backedges from the region when only one of the loop blocks uses the register. Previously, we would include the backedge in the region if the loop preheader and the loop latch both used the register, but the loop header didn't. When both the header and latch blocks use the register, we still keep it live on the backedge. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136832 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-03Fix some warnings from Clang in release builds:Chandler Carruth
lib/CodeGen/RegAllocGreedy.cpp:1176:18: warning: unused variable 'B' [-Wunused-variable] if (unsigned B = Cand.getBundles(BundleCand, BestCand)) { ^ lib/CodeGen/RegAllocGreedy.cpp:1188:18: warning: unused variable 'B' [-Wunused-variable] if (unsigned B = Cand.getBundles(BundleCand, 0)) { ^ git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136831 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-03Fix typo in #include which revealed in the case-sensitive filesystem.Jakub Staszak
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136828 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-03Use MachineBranchProbabilityInfo in If-Conversion instead of its own heuristics.Jakub Staszak
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136826 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-03Add more constantness in BlockFrequencyInfo.Jakub Staszak
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136816 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-03New approach to r136737: insert the necessary fences for atomic ops in ↵Eli Friedman
platform-independent code, since a bunch of platforms (ARM, Mips, PPC, Alpha are the relevant targets here) need to do essentially the same thing. I think this completes the basic CodeGen for atomicrmw and cmpxchg. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136813 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-03Some revisions to Devang's change r136759 for merged global debug info.Bob Wilson
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136802 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-03Use byte offset, instead of element number, to access merged global.Devang Patel
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136759 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-02Use the precomputed def presence in RAGreedy::calcSpillCost.Jakob Stoklund Olesen
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136742 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-02Inform SpillPlacement about blocks with defs.Jakob Stoklund Olesen
This information is not used for anything yet. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136741 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-02Rename {First,Last}Use to {First,Last}Instr.Jakob Stoklund Olesen
With a 'FirstDef' field right there, it is very confusing that FirstUse refers to an instruction that may be a def. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136739 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-02Add a BlockInfo::FirstDef field.Jakob Stoklund Olesen
This is either an invalid SlotIndex, or valno->def for the first value defined inside the block. PHI values are not counted as defined inside the block. The FirstDef field will be used when estimating the cost of spilling around a block. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136736 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-02Delete BlockInfo::LiveThrough. It wasn't used any more.Jakob Stoklund Olesen
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136735 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-02Extend the SpillPlacement interface with two new features.Jakob Stoklund Olesen
The PrefBoth constraint is used for blocks that ideally want a live-in value both on the stack and in a register. This would be used by a block that has a use before interference forces a spill. Secondly, add the ChangesValue flag to BlockConstraint. This tells SpillPlacement if a live-in value on the stack can be reused as a live-out stack value for free. If the block redefines the virtual register, a spill would be required for that. This extra information will be used by SpillPlacement to more accurately calculate spill costs when a value can exist both on the stack and in a register. The simplest example is a basic block that reads the virtual register, but doesn't change its value. Spilling around such a block requires a reload, but no spill in the block. The spiller already knows this, but the spill placer doesn't. That can sometimes lead to suboptimal regions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136731 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-02Don't create a ridiculous EXTRACT_ELEMENT. PR10563.Eli Friedman
The testcase looks extremely fragile, so I'm adding an assertion which should catch any cases like this. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136711 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-01Remove an unnecessary cast.Jay Foad
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136609 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-31Add the 'resume' instruction for the new EH rewrite.Bill Wendling
This adds the 'resume' instruction class, IR parsing, and bitcode reading and writing. The 'resume' instruction resumes propagation of an existing (in-flight) exception whose unwinding was interrupted with a 'landingpad' instruction (to be added later). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136589 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-31Time the emission of debug values.Jakob Stoklund Olesen
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136584 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-30Revert r136528 "Enable compact region splitting by default."Jakob Stoklund Olesen
While this generally helped x86-64, there was some large regressions for i386. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136571 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-30Revert r136253, r136263, r136269, r136313, r136325, r136326, r136329, r136338,Bill Wendling
r136339, r136341, r136369, r136387, r136392, r136396, r136429, r136430, r136444, r136445, r136446, r136253 pending review. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136556 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-30Revert "Don't check liveness of unallocatable registers."Jakob Stoklund Olesen
The ARM target depends on CPSR liveness being tracked after register allocation. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136548 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-29Don't check liveness of unallocatable registers.Jakob Stoklund Olesen
This includes registers like EFLAGS and ST0-ST7. We don't check for liveness issues in the verifier and scavenger because registers will never be allocated from these classes. While in SSA form, we do care about the liveness of unallocatable unreserved registers. Liveness of EFLAGS and ST0 neds to be correct for MachineDCE and MachineSinking. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136541 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-29Check for multiple defs in the machine code verifier.Jakob Stoklund Olesen
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136535 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-29Add an isSSA() flag to MachineRegisterInfo.Jakob Stoklund Olesen
This flag is true from isel to register allocation when the machine function is required to be in SSA form. The TwoAddressInstructionPass and PHIElimination passes clear the flag. The SSA flag wil be used by the machine code verifier to check for SSA form, and eventually an assertion can enforce it in +Asserts builds. This will catch the common target error of creating machine code with multiple defs of a virtual register. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136532 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-29Do not lose branch weights when lowering SwitchInst.Jakub Staszak
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136529 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-29Enable compact region splitting by default.Jakob Stoklund Olesen
This helps generate better code in functions with high register pressure. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136528 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-29Remove unneeded const_cast.Jakub Staszak
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136506 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-29Fix a lot of typos, improve (but not necessarily fix) grammaros and reflow someNick Lewycky
lines. No functionality change. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136458 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-29Misc optimizer+codegen work for 'cmpxchg' and 'atomicrmw'. They appear to beEli Friedman
working on x86 (at least for trivial testcases); other architectures will need more work so that they actually emit the appropriate instructions for orderings stricter than 'monotonic'. (As far as I can tell, the ARM, PPC, Mips, and Alpha backends need such changes.) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136457 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-29Use the pointer type size.Bill Wendling
With this, we can now compile a simple EH program. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136446 91177308-0d34-0410-b5e6-96231b3b80d8
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