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2011-06-12Really fix the fall-through logic.Rafael Espindola
Add a triple to the tests. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132885 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-12Fix silly bug I introduce in the previous commit. Fixes debug builds.Rafael Espindola
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132883 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-12AnalyzeBranch doesn't change which successors a bb has, just the orderRafael Espindola
we try to branch to them. Before we were creating successor lists with duplicated entries. Fixing that found a bug in isBlockOnlyReachableByFallthrough that would causes it to return the wrong answer for ----------- ... jne foo jmp bar foo: ---------- git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132882 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-11Revert r132871.Chad Rosier
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132872 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-11Typo.Chad Rosier
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132871 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-1080-col cleanups.Eric Christopher
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132863 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-10Removed tabs. Also fixed my editor...Rafael Espindola
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132857 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-10Rename the ParmContext enum values to make a bit more sense and add a smallCameron Zwarich
comment on their meaning. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132854 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-10Remove tabs.Cameron Zwarich
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132853 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-10Remove a pointless const_cast.Cameron Zwarich
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132852 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-10Remove duplicated test.Rafael Espindola
Thanks Bob Wilson for noticing it! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132851 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-10Ensure that EmitGlobalVariable is correctly differentiating between declarationsChad Rosier
and definitions when emitting global variables. This was causing global declarations to be emitted as if they were definitions. Fixes <rdar://problem/9429892>. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132825 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-09Make the optional verification step more strict.Rafael Espindola
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132822 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-09Avoid a gcc warning about multiline comments.Rafael Espindola
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132821 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-09On last fix to the early tail duplication.Rafael Espindola
With this I am able to bootstrap clang with early tail duplication enabled for any small bb and setting tail-dup-size to a relatively large value(8) to stress this code. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132816 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-09Also consider phi nodes when deciding if a register is live out.Rafael Espindola
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132814 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-09Change this DAGCombine to build AND of SHR instead of SHR of AND; this ↵Eli Friedman
matches the ordering we prefer in instcombine. Part of rdar://9562809. The potential DAGCombine which enforces this more generally messes up some other very fragile patterns, so I'm leaving that alone, at least for now. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132809 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-09AnalyzeBranch modifies the bb, but we don't want to modify a bb withRafael Espindola
eh edges. Swap the order of the checks to avoid it. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132806 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-09A PHI in this basic block is a use in another basic block.Rafael Espindola
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132805 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-09Refactor some checks into shouldTailDuplicate. Update comments.Rafael Espindola
No functionality change. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132798 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-09Recommit r132764 since it didn't cause the windows buildbot failures.Eric Christopher
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132776 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-09Temporarily revert 132764 to see if it fixes the Windows buildbot.Eric Christopher
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132771 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-09If the alignment of the byval argument is greater than the alignmentEric Christopher
of the frame then increase the maximum alignment of the frame to match. Fixes PR6965 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132764 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-08Add a parameter to CCState so that it can access the MachineFunction.Eric Christopher
No functional change. Part of PR6965 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132763 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-08Remove a temporary test case probe in CheckForLiveRegDef.Andrew Trick
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132751 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-08Fix count.Rafael Espindola
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132749 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-08Count how many phis we are creating.Rafael Espindola
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132748 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-07Fix an issue where the two-address conversion pass incorrectly rewrites untiedCameron Zwarich
operands to an early clobber register. This fixes <rdar://problem/9566076>. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132738 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-07Fix a silly error I introduce in r131951.Rafael Espindola
Fixes PR10095. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132735 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-07Fix a merge bug in preRAsched for handling physreg aliases.Andrew Trick
I've been sitting on this long enough trying to find a test case. I think the fix should go in now, but I'll keep working on the test case. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132701 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-06Simplify local live range splitting's safeguard to fix PR10070.Jakob Stoklund Olesen
When local live range splitting creates a live range with the same number of instructions as the old range, mark it as RS_Local. When such a range is seen again, require that it be split in a way that reduces the number of instructions. That guarantees we are making progress while still being able to perform 3 -> 2+3 splits as required by PR10070. This also means that the PrevSlot map is no longer needed. This was also used to estimate new spill weights, but that is no longer necessary after slotIndexes::insertMachineInstrInMaps() got the extra Late insertion argument. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132697 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-06Get allocation orders from RegisterClassInfo when possible.Jakob Stoklund Olesen
Only target-dependent hints require callbacks. The RCI allocation order has CSR aliases last according to their order of appearance in the getCalleeSavedRegs list. This can depend on the calling convention. This way, AllocationOrder::next doesn't have to check for reserved registers, and CSRs are always allocated last, even with weird calling conventions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132690 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-06Add methods to support the integer-promotion of vector types. Methods toNadav Rotem
legalize SDNodes such as BUILD_VECTOR, EXTRACT_VECTOR_ELT, etc. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132689 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-06Avoid FGETSIGN of 80-bit types. Fixes PR10085.Stuart Hastings
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132681 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-06Don't try to be clever, just preserve the target's allocation order.Jakob Stoklund Olesen
The order of registers returned by getCalleeSavedRegs is used to lay out the fixed stack slots for CSRs. Some targets like their CSRs used from one end, and some targets want them used from the other end. When computing an allocation order, simply preserve the relative ordering of CSRs that the target specifies in its allocation order. Reordering CSRs would break some targets, ARM in particular. We still place volatiles before the CSRs, providing slightly better results with different calling conventions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132680 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-06PR10077: fix fast-isel of extractvalue of aggregate constants.Eli Friedman
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132676 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-05Use path API for path concatenation.Benjamin Kramer
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132668 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-04TypeLegalizer: Add support for passing of vector-promoted types in registers ↵Nadav Rotem
(copyFromParts/copyToParts). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132649 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-04TypeLegalizer: Fix a bug in the promotion of elements of integer vectors.Nadav Rotem
(only happens when using the -promote-elements option). The correct legalization order is to first try to promote element. Next, we try to widen vectors. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132648 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-03Switch AllocationOrder to using RegisterClassInfo instead of a BitVectorJakob Stoklund Olesen
of reserved registers. Use RegisterClassInfo in RABasic as well. This slightly changes som allocation orders because RegisterClassInfo puts CSR aliases last. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132581 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-03Preserve the original ordering when a CSR has multiple aliases.Jakob Stoklund Olesen
Previously, these aliases would be ordered alphabetically. (BH, BL) Print out the computed allocation orders. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132580 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-03Add a TODO about memory operands.Eric Christopher
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132559 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-02Avoid calling TRI->getAllocatableSet in RAFast.Jakob Stoklund Olesen
When compiling a program with lots of small functions like 483.xalancbmk, this makes RAFast 11% faster. Add some comments to clarify the difference between unallocatable and reserved registers. It's quite subtle. The fast register allocator depends on EFLAGS' not being allocatable on x86. That way it can completely avoid tracking liveness, and it won't mind when there are multiple uses of a single def. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132514 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-02Have LowerOperandForConstraint handle multiple character constraints.Eric Christopher
Part of rdar://9119939 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132510 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-02Make it possible to have unallocatable register classes.Jakob Stoklund Olesen
Some register classes are only used for instruction operand constraints. They should never be used for virtual registers. Previously, those register classes were given an empty allocation order, but now you can say 'let isAllocatable=0' in the register class definition. TableGen calculates if a register is part of any allocatable register class, and makes that information available in TargetRegisterDesc::inAllocatableClass. The goal here is to eliminate use cases for overriding allocation_order_* methods. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132508 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-02Just use a SmallVector.Jakob Stoklund Olesen
I was confused whether new uint8_t[] would zero-initialize the returned array, and it seems that so is gcc-4.0. This should fix the test failures on darwin 9. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132500 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-02Remove dead code.Devang Patel
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132488 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-02Update DBG_VALUEs while breaking anti dependencies.Devang Patel
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132487 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-02During post RA scheduling, do not try to chase reg defs. to preserve ↵Devang Patel
DBG_VALUEs. This approach has several downsides, for example, it does not work when dbg value is a constant integer, it does not work if reg is defined more than once, it places end of debug value range markers in the wrong place. It even causes misleading incorrect debug info when duplicate DBG_VALUE instructions point to same reg def. Instead, use simpler approach and let DBG_VALUE follow its predecessor instruction. After live debug value analysis pass, all DBG_VALUE instruction are placed at the right place. Thanks Jakob for the hint! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132483 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-02Revert 132424 to fix PR10068.Rafael Espindola
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132479 91177308-0d34-0410-b5e6-96231b3b80d8
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