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2009-10-01All callee-saved registers are live-out of a return block.David Goodwin
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83223 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-01Remove neonfp attribute and instead set default based on CPU string. Add ↵David Goodwin
-arm-use-neon-fp to override the default. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83218 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-01Restore the -post-RA-scheduler flag as an override for the target ↵David Goodwin
specification. Remove -mattr for setting PostRAScheduler enable and instead use CPU string. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83215 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-01Add support to extract lexical scope information from DebugLoc attached with ↵Devang Patel
an machine instruction. This is not yet enabled. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83210 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-01Use MachineFrameInfo.getPristineRegs() to determine which callee-saved ↵David Goodwin
registers are available for anti-dependency breaking. Some cleanup. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83208 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-01 Record first and last instruction of a scope in DbgScope.Devang Patel
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83207 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-01Observe hasExtraSrcRegAllocReq and hasExtraDefRegAllocReq. Do not changeEvan Cheng
operands of instructions with these properties while breaking anti-dep. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83198 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-01Add another MDNode into DebugLocTuple. This will be used to keep track of ↵Devang Patel
inlined functions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83190 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-01If location info is attached with an instruction then keep track of alloca ↵Devang Patel
slots used by a variable. This info will be used by AsmPrinter to emit debug info for variables. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83189 91177308-0d34-0410-b5e6-96231b3b80d8
2009-09-30Use MachineInstr as an processDebugLoc() argument.Devang Patel
This will allow processDebugLoc() to handle scopes for DWARF debug info. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83183 91177308-0d34-0410-b5e6-96231b3b80d8
2009-09-30Use MDNode * directly as an RecordSourceLine() argument.Devang Patel
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83182 91177308-0d34-0410-b5e6-96231b3b80d8
2009-09-30Remove dead code.Devang Patel
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83181 91177308-0d34-0410-b5e6-96231b3b80d8
2009-09-30Add a new virtual EmitStartOfAsmFile method to the AsmPrinter and use thisBob Wilson
to emit target-specific things at the beginning of the asm output. This fixes a problem for PPC, where the text sections are not being kept together as expected. The base class doInitialization code calls DW->BeginModule() which emits a bunch of DWARF section directives. The PPC doInitialization code then emits all the TEXT section directives, with the intention that they will be kept together. But as I understand it, the Darwin assembler treats the default TEXT section as a special case and moves it to the beginning of the file, which means that all those DWARF sections are in the middle of the text. With this change, the EmitStartOfAsmFile hook is called before the DWARF section directives are emitted, so that all the PPC text section directives come out right at the beginning of the file. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83176 91177308-0d34-0410-b5e6-96231b3b80d8
2009-09-30Fix a comment.Bob Wilson
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83171 91177308-0d34-0410-b5e6-96231b3b80d8
2009-09-30Silence comparison always false warning in -Asserts mode.Reid Kleckner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83164 91177308-0d34-0410-b5e6-96231b3b80d8
2009-09-30Add additional assert() to verify no extraneous use of a scavenged register.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83163 91177308-0d34-0410-b5e6-96231b3b80d8
2009-09-30Fix integer overflow in instruction scheduling. This can happen if we haveReid Kleckner
basic blocks that are so long that their size overflows a short. Also assert that overflow does not happen in the future, as requested by Evan. This fixes PR4401. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83159 91177308-0d34-0410-b5e6-96231b3b80d8
2009-09-30Add a target hook to add pre- post-regalloc scheduling passes.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83144 91177308-0d34-0410-b5e6-96231b3b80d8
2009-09-30replace TRI->isVirtualRegister() with TargetRegisterInfo::isVirtualRegister()Jim Grosbach
per customary usage git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83137 91177308-0d34-0410-b5e6-96231b3b80d8
2009-09-30fix compiler warningJim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83132 91177308-0d34-0410-b5e6-96231b3b80d8
2009-09-30Simplify.Devang Patel
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83123 91177308-0d34-0410-b5e6-96231b3b80d8
2009-09-30Remove -post-RA-schedule flag and add a TargetSubtarget method to enable ↵David Goodwin
post-register-allocation scheduling. By default it is off. For ARM, enable/disable with -mattr=+/-postrasched. Enable by default for cortex-a8. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83122 91177308-0d34-0410-b5e6-96231b3b80d8
2009-09-30Add a way for a frontend to generate more complex dwarf locationMike Stump
information. This allows arbitrary code involving DW_OP_plus_uconst and DW_OP_deref. The scheme allows for easy extention to include, any, or all of the DW_OP_ opcodes. I thought about just exposing all of them, but, wasn't sure if people wanted the dwarf opcodes exposed in the api. Is that a layering violation? With this scheme, the entire existing block scheme used by llvm-gcc can be switched over to the new scheme. I think that would be cleaner, as then the compiler specific bits are not present in llvm proper. Before the old code can be yanked however, similar code in clang would have to be removed. Next up, more testing. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83120 91177308-0d34-0410-b5e6-96231b3b80d8
2009-09-29Additional check for regno==0Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83103 91177308-0d34-0410-b5e6-96231b3b80d8
2009-09-29Remove unnecessary cast.Devang Patel
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83100 91177308-0d34-0410-b5e6-96231b3b80d8
2009-09-29Remove std::string uses from DebugInfo interface.Devang Patel
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83083 91177308-0d34-0410-b5e6-96231b3b80d8
2009-09-29Simplify the tracking of virtual frame index registers. Ranges cannot overlap,Jim Grosbach
so a simple "current register" will suffice. Also add some additional sanity-checking assertions to make sure things are as we expect. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83081 91177308-0d34-0410-b5e6-96231b3b80d8
2009-09-29Moving register scavenging to a post pass results in virtual registers inJim Grosbach
the instruction we're scavenging for. The scavenger needs to know to avoid them when analyzing register usage. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83077 91177308-0d34-0410-b5e6-96231b3b80d8
2009-09-28s/class Metadata/class MetadataContext/gDevang Patel
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83019 91177308-0d34-0410-b5e6-96231b3b80d8
2009-09-28Do not use global typedef for MDKindID.Devang Patel
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83016 91177308-0d34-0410-b5e6-96231b3b80d8
2009-09-28Use KILL instead of IMPLICIT_DEF in LowerSubregs pass.Jakob Stoklund Olesen
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83007 91177308-0d34-0410-b5e6-96231b3b80d8
2009-09-28Use VerifySchedule instead of doing the work manually.Dan Gohman
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82995 91177308-0d34-0410-b5e6-96231b3b80d8
2009-09-28Coalescer should not delete extract_subreg, insert_subreg, and subreg_to_reg ofEvan Cheng
physical registers. This is especially critical for the later two since they start the live interval of a super-register. e.g. %DO<def> = INSERT_SUBREG %D0<undef>, %S0<kill>, 1 If this instruction is eliminated, the register scavenger will not be happy as D0 is not defined previously. This fixes PR5055. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82968 91177308-0d34-0410-b5e6-96231b3b80d8
2009-09-27Use explicit structs instead of std::pair to map callee saved regs to spill ↵Tilmann Scheller
slots. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82909 91177308-0d34-0410-b5e6-96231b3b80d8
2009-09-26Convert comparisons like (x == infinity) to (x >= infinity) on targetsDan Gohman
where FCMP_OEQ is not legal and FCMP_OGE is, such as x86. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82861 91177308-0d34-0410-b5e6-96231b3b80d8
2009-09-26Don't hoist or sink instructions with physreg uses if the physreg isDan Gohman
allocatable. Even if it doesn't appear to have any defs, it may latter on after register allocation. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82834 91177308-0d34-0410-b5e6-96231b3b80d8
2009-09-25Unbreak MachineLICM for instructions that reference RIP on x86-64 too.Dan Gohman
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82825 91177308-0d34-0410-b5e6-96231b3b80d8
2009-09-25Move MachineMemOperand::getAlignment out of line, to avoid needingDan Gohman
MathExtras.h in MachineMemOperand.h. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82822 91177308-0d34-0410-b5e6-96231b3b80d8
2009-09-25Remove unused variable.Daniel Dunbar
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82821 91177308-0d34-0410-b5e6-96231b3b80d8
2009-09-25Fix MachineSink to be able to sink instructions that use physical registersDan Gohman
which have no defs anywhere in the function. In particular, this fixes sinking of instructions that reference RIP on x86-64, which is currently being modeled as a register. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82815 91177308-0d34-0410-b5e6-96231b3b80d8
2009-09-25Simplify a few more uses of reg_iterator.Dan Gohman
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82812 91177308-0d34-0410-b5e6-96231b3b80d8
2009-09-25Simplify this code by using use_iterator instead of reg_iteratorDan Gohman
and skipping the defs. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82811 91177308-0d34-0410-b5e6-96231b3b80d8
2009-09-25Flip -disable-post-RA-scheduler to -post-RA-scheduler.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82803 91177308-0d34-0410-b5e6-96231b3b80d8
2009-09-25Improve MachineMemOperand handling.Dan Gohman
- Allocate MachineMemOperands and MachineMemOperand lists in MachineFunctions. This eliminates MachineInstr's std::list member and allows the data to be created by isel and live for the remainder of codegen, avoiding a lot of copying and unnecessary translation. This also shrinks MemSDNode. - Delete MemOperandSDNode. Introduce MachineSDNode which has dedicated fields for MachineMemOperands. - Change MemSDNode to have a MachineMemOperand member instead of its own fields with the same information. This introduces some redundancy, but it's more consistent with what MachineInstr will eventually want. - Ignore alignment when searching for redundant loads for CSE, but remember the greatest alignment. Target-specific code which previously used MemOperandSDNodes with generic SDNodes now use MemIntrinsicSDNodes, with opcodes in a designated range so that the SelectionDAG framework knows that MachineMemOperand information is available. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82794 91177308-0d34-0410-b5e6-96231b3b80d8
2009-09-25Rename getTargetNode to getMachineNode, for consistency with theDan Gohman
naming scheme used in SelectionDAG, where there are multiple kinds of "target" nodes, but "machine" nodes are nodes which represent a MachineInstr. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82790 91177308-0d34-0410-b5e6-96231b3b80d8
2009-09-25Make sure sin, cos, sqrt calls are marked readonlyDale Johannesen
before producing FSIN, FCOS, FSQRT. If they aren't so marked we have to assume they might set errno. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82781 91177308-0d34-0410-b5e6-96231b3b80d8
2009-09-25Generate FSQRT from calls to the sqrt function, whichDale Johannesen
allows appropriate backends to generate a sqrt instruction. On x86, this isn't done at -O0 because we go through FastISel instead. This is a behavior change from before this series of sqrt patches started. I think this is OK considering that compile speed is most important at -O0, but could be convinced otherwise. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82778 91177308-0d34-0410-b5e6-96231b3b80d8
2009-09-25pr4926: ARM requires the stack pointer to be aligned, even for leaf functions.Bob Wilson
For the AAPCS ABI, SP must always be 4-byte aligned, and at any "public interface" it must be 8-byte aligned. For the older ARM APCS ABI, the stack alignment is just always 4 bytes. For X86, we currently align SP at entry to a function (e.g., to 16 bytes for Darwin), but no stack alignment is needed at other times, such as for a leaf function. After discussing this with Dan, I decided to go with the approach of adding a new "TransientStackAlignment" field to TargetFrameInfo. This value specifies the stack alignment that must be maintained even in between calls. It defaults to 1 except for ARM, where it is 4. (Some other targets may also want to set this if they have similar stack requirements. It's not currently required for PPC because it sets targetHandlesStackFrameRounding and handles the alignment in target-specific code.) The existing StackAlignment value specifies the alignment upon entry to a function, which is how we've been using it anyway. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82767 91177308-0d34-0410-b5e6-96231b3b80d8
2009-09-25Fix combiner-aa issue with bases which are different, but can alias.Nate Begeman
Previously, it treated GV+28 GV+0 as different bases, and assumed they could not alias. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82753 91177308-0d34-0410-b5e6-96231b3b80d8
2009-09-25Add a version of dumpr() that has a SelectionDAG* argument.Dan Gohman
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82742 91177308-0d34-0410-b5e6-96231b3b80d8
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