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2008-03-13Remove unused options.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48319 91177308-0d34-0410-b5e6-96231b3b80d8
2008-03-13Refactor some code out of MachineSink into a MachineInstr query.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48311 91177308-0d34-0410-b5e6-96231b3b80d8
2008-03-12Experimental scheduler change to schedule / coalesce the copies added for ↵Evan Cheng
function livein's. Take 2008-03-10-RegAllocInfLoop.ll, the schedule looks like this after these copies are inserted: entry: 0x12049d0, LLVM BB @0x1201fd0, ID#0: Live Ins: %EAX %EDX %ECX %reg1031<def> = MOVPC32r 0 %reg1032<def> = ADD32ri %reg1031, <es:_GLOBAL_OFFSET_TABLE_>, %EFLAGS<imp-def> %reg1028<def> = MOV32rr %EAX %reg1029<def> = MOV32rr %EDX %reg1030<def> = MOV32rr %ECX %reg1027<def> = MOV8rm %reg0, 1, %reg0, 0, Mem:LD(1,1) [0x1201910 + 0] %reg1025<def> = MOV32rr %reg1029 %reg1026<def> = MOV32rr %reg1030 %reg1024<def> = MOV32rr %reg1028 The copies unnecessarily increase register pressure and it will end up requiring a physical register to be spilled. With -schedule-livein-copies: entry: 0x12049d0, LLVM BB @0x1201fa0, ID#0: Live Ins: %EAX %EDX %ECX %reg1031<def> = MOVPC32r 0 %reg1032<def> = ADD32ri %reg1031, <es:_GLOBAL_OFFSET_TABLE_>, %EFLAGS<imp-def> %reg1024<def> = MOV32rr %EAX %reg1025<def> = MOV32rr %EDX %reg1026<def> = MOV32rr %ECX %reg1027<def> = MOV8rm %reg0, 1, %reg0, 0, Mem:LD(1,1) [0x12018e0 + 0] Much better! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48307 91177308-0d34-0410-b5e6-96231b3b80d8
2008-03-12Initial soft-float support for LegalizeTypes. I rewroteDuncan Sands
the fcopysign expansion from LegalizeDAG to get rid of what seems to be a bug: the use of sign extension means that when copying the sign bit from an f32 to an f64, the upper 32 bits of the f64 (now an i64) are set, not just the top bit... I also generalized it to work for any sized floating point types, and removed the bogosity: SDOperand Mask1 = (SrcVT == MVT::f64) ? DAG.getConstantFP(BitsToDouble(1ULL << 63), SrcVT) : DAG.getConstantFP(BitsToFloat(1U << 31), SrcVT); Mask1 = DAG.getNode(ISD::BIT_CONVERT, SrcNVT, Mask1); (here SrcNVT is an integer with the same size as SrcVT). As far as I can see this takes a 1 << 63, converts to a double, converts that to a floating point constant then converts that to an integer constant, ending up with... 1 << 63 as an integer constant! So I just generate this integer constant directly. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48305 91177308-0d34-0410-b5e6-96231b3b80d8
2008-03-12Change VirtRegMap's dump to dump to cerr, not DOUT, so that itDan Gohman
can be called from within a debuger without having -debug specified on the command-line. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48298 91177308-0d34-0410-b5e6-96231b3b80d8
2008-03-12Fix typos in comments.Dan Gohman
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48297 91177308-0d34-0410-b5e6-96231b3b80d8
2008-03-12Fix typo.Duncan Sands
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48295 91177308-0d34-0410-b5e6-96231b3b80d8
2008-03-12Don't try to extract an i32 from an f64. ThisDuncan Sands
getCopyToParts problem was noticed by the new LegalizeTypes infrastructure. In order to avoid this kind of thing in the future I've added a check that EXTRACT_ELEMENT is only used with integers. Once LegalizeTypes is up and running most likely BUILD_PAIR and EXTRACT_ELEMENT can be removed, in favour of using apints instead. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48294 91177308-0d34-0410-b5e6-96231b3b80d8
2008-03-12Clean up my own mess.Evan Cheng
X86 lowering normalize vector 0 to v4i32. However DAGCombine can fold (sub x, x) -> 0 after legalization. It can create a zero vector of a type that's not expected (e.g. v8i16). We don't want to disable the optimization since leaving a (sub x, x) is really bad. Add isel patterns for other types of vector 0 to ensure correctness. It's highly unlikely to happen other than in bugpoint reduced test cases. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48279 91177308-0d34-0410-b5e6-96231b3b80d8
2008-03-12We also need to collect the VN IDs for the PHI instructions for later updating.Owen Anderson
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48278 91177308-0d34-0410-b5e6-96231b3b80d8
2008-03-12When we're determining what registers to coallesce, track the VNInfo IDs for ↵Owen Anderson
the definitions that feed the PHI instructions. We'll need these IDs in order to update LiveIntervals properly. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48277 91177308-0d34-0410-b5e6-96231b3b80d8
2008-03-12Total brain cramp.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48274 91177308-0d34-0410-b5e6-96231b3b80d8
2008-03-12Set NextMII after issuing a physical register spill.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48263 91177308-0d34-0410-b5e6-96231b3b80d8
2008-03-12Minor debug output bug.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48261 91177308-0d34-0410-b5e6-96231b3b80d8
2008-03-11Correctly propagate thread-local flag from aliasee to alias. This fixes PR2137Anton Korobeynikov
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48257 91177308-0d34-0410-b5e6-96231b3b80d8
2008-03-11Use PassManagerBase instead of FunctionPassManager for functionsDan Gohman
that merely add passes. This allows them to be used with either FunctionPassManager or PassManager, or even with a custom new kind of pass manager. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48256 91177308-0d34-0410-b5e6-96231b3b80d8
2008-03-11Honour aliases visibility during asm emissionAnton Korobeynikov
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48249 91177308-0d34-0410-b5e6-96231b3b80d8
2008-03-11Transfer physical register spill info when load / store folding happens.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48246 91177308-0d34-0410-b5e6-96231b3b80d8
2008-03-11Use the correct value for InSignBit.Dan Gohman
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48245 91177308-0d34-0410-b5e6-96231b3b80d8
2008-03-11Initial codegen support for functions and calls with multiple return values.Dan Gohman
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48244 91177308-0d34-0410-b5e6-96231b3b80d8
2008-03-11Recommitting parts of r48130. These do not appear to cause the observed ↵Christopher Lamb
failures. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48223 91177308-0d34-0410-b5e6-96231b3b80d8
2008-03-11Use TargetRegisterInfo::getPhysicalRegisterRegClass. Remove duplicated code.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48221 91177308-0d34-0410-b5e6-96231b3b80d8
2008-03-11When the register allocator runs out of registers, spill a physical register ↵Evan Cheng
around the def's and use's of the interval being allocated to make it possible for the interval to target a register and spill it right away and restore a register for uses. This likely generates terrible code but is before than aborting. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48218 91177308-0d34-0410-b5e6-96231b3b80d8
2008-03-11Some LegalizeTypes code factorization and minorDuncan Sands
enhancements. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48215 91177308-0d34-0410-b5e6-96231b3b80d8
2008-03-11compile: double test() {}Chris Lattner
into: _test: fldz ret instead of: _test: subl $12, %esp #IMPLICIT_DEF %xmm0 movsd %xmm0, (%esp) fldl (%esp) addl $12, %esp ret git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48213 91177308-0d34-0410-b5e6-96231b3b80d8
2008-03-11variadic instructions don't have operand info for variadic arguments.Chris Lattner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48208 91177308-0d34-0410-b5e6-96231b3b80d8
2008-03-11Generalize ExpandIntToFP to handle the case where the operand is legalDan Gohman
and it's the result that requires expansion. This code is a little confusing because the TargetLoweringInfo tables for [US]INT_TO_FP use the operand type (the integer type) rather than the result type. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48206 91177308-0d34-0410-b5e6-96231b3b80d8
2008-03-11If a register operand comes from the variadic part of a node, don'tChris Lattner
verify the register constraint matches what the instruction expects. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48205 91177308-0d34-0410-b5e6-96231b3b80d8
2008-03-11Temporarily revert 48175.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48204 91177308-0d34-0410-b5e6-96231b3b80d8
2008-03-11More APInt-ification.Dan Gohman
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48201 91177308-0d34-0410-b5e6-96231b3b80d8
2008-03-10Correctly clone FlaggedNodes.Dan Gohman
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48196 91177308-0d34-0410-b5e6-96231b3b80d8
2008-03-10APInt-ify this.Dan Gohman
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48194 91177308-0d34-0410-b5e6-96231b3b80d8
2008-03-10Implement more support for fp-to-i128 and i128-to-fp conversions. Dan Gohman
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48189 91177308-0d34-0410-b5e6-96231b3b80d8
2008-03-10If the register allocator ran out of registers, just abort for now.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48175 91177308-0d34-0410-b5e6-96231b3b80d8
2008-03-10Fix mul expansion to check the correct number of bits forDan Gohman
zero extension when checking if an unsigned multiply is safe. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48171 91177308-0d34-0410-b5e6-96231b3b80d8
2008-03-10Somewhat better solution.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48170 91177308-0d34-0410-b5e6-96231b3b80d8
2008-03-10Default ISD::PREFETCH to expand.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48169 91177308-0d34-0410-b5e6-96231b3b80d8
2008-03-10Revert 48125, 48126, and 48130 for now to unbreak some x86-64 tests.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48167 91177308-0d34-0410-b5e6-96231b3b80d8
2008-03-10Give TargetLowering::getSetCCResultType() a parameter so that ISD::SETCC'sScott Michel
return ValueType can depend its operands' ValueType. This is a cosmetic change, no functionality impacted. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48145 91177308-0d34-0410-b5e6-96231b3b80d8
2008-03-10Minor cleanup. No functionality change.Bill Wendling
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48142 91177308-0d34-0410-b5e6-96231b3b80d8
2008-03-10- Fix a subtle bug in RemoveCopyByCommutingDef. ALR is the live range where ↵Evan Cheng
the source is defined; BLR is the live range which is defined by the copy. If ALR and BLR overlaps and end of BLR extends beyond end of ALR, e.g. A = or A, B ... B = A ... C = A<kill> ... = B then do not add kills of A to the newly created B interval. - Also fix some kill info update bug. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48141 91177308-0d34-0410-b5e6-96231b3b80d8
2008-03-10DohEvan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48140 91177308-0d34-0410-b5e6-96231b3b80d8
2008-03-10Move StrongPHIElimination after live interval analysis. This will make ↵Owen Anderson
things happier down the road. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48138 91177308-0d34-0410-b5e6-96231b3b80d8
2008-03-10Avoid creating BUILD_VECTOR of all zero elements of "non-normalized" type ↵Evan Cheng
(e.g. v8i16 on x86) after legalizer. Instruction selection does not expect to see them. In all likelihood this can only be an issue in a bugpoint reduced test case. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48136 91177308-0d34-0410-b5e6-96231b3b80d8
2008-03-10Allow insert_subreg into implicit, target-specific values. Christopher Lamb
Change insert/extract subreg instructions to be able to be used in TableGen patterns. Use the above features to reimplement an x86-64 pseudo instruction as a pattern. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48130 91177308-0d34-0410-b5e6-96231b3b80d8
2008-03-10Increase ISD::ParamFlags to 64 bits. Increase the ByValSizeDale Johannesen
field to 32 bits, thus enabling correct handling of ByVal structs bigger than 0x1ffff. Abstract interface a bit. Fixes gcc.c-torture/execute/pr23135.c and gcc.c-torture/execute/pr28982b.c in gcc testsuite (were ICE'ing on ppc32, quietly producing wrong code on x86-32.) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48122 91177308-0d34-0410-b5e6-96231b3b80d8
2008-03-09remove an extraneous (and ugly) default argument, thanks Duncan.Chris Lattner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48117 91177308-0d34-0410-b5e6-96231b3b80d8
2008-03-09fp_round's produced by getCopyFromParts should always be exact, becauseChris Lattner
they are produced by calls (which are known exact) and by cross block copies which are known to be produced by extends. This improves: define double @test2() { %tmp85 = call double asm sideeffect "fld0", "={st(0)}"() ret double %tmp85 } from: _test2: subl $20, %esp # InlineAsm Start fld0 # InlineAsm End fstpl 8(%esp) movsd 8(%esp), %xmm0 movsd %xmm0, (%esp) fldl (%esp) addl $20, %esp #FP_REG_KILL ret to: _test2: # InlineAsm Start fld0 # InlineAsm End #FP_REG_KILL ret by avoiding a f64 <-> f80 trip git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48108 91177308-0d34-0410-b5e6-96231b3b80d8
2008-03-09teach X86InstrInfo::copyRegToReg how to copy into ST(0) from Chris Lattner
an RFP register class. Teach ScheduleDAG how to handle CopyToReg with different src/dst reg classes. This allows us to compile trivial inline asms that expect stuff on the top of x87-fp stack. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48107 91177308-0d34-0410-b5e6-96231b3b80d8
2008-03-09Add ScheduleDAG support for copytoreg where the src/dst register areChris Lattner
in different register classes, e.g. copy of ST(0) to RFP*. This gets some really trivial inline asm working that plops things on the top of stack (PR879) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48105 91177308-0d34-0410-b5e6-96231b3b80d8
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