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2008-02-27Handle load/store of misaligned vectors that are the Dale Johannesen
same size as an int type by doing a bitconvert of load/store of the int type (same algorithm as floating point). This makes them work for ppc Altivec. There was some code that purported to handle loads of (some) vectors by splitting them into two smaller vectors, but getExtLoad rejects subvector loads, so this could never have worked; the patch removes it. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47696 91177308-0d34-0410-b5e6-96231b3b80d8
2008-02-27Fix a bug in dead spill slot elimination.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47687 91177308-0d34-0410-b5e6-96231b3b80d8
2008-02-27Remove the `else', at Evan's insistence.Dan Gohman
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47686 91177308-0d34-0410-b5e6-96231b3b80d8
2008-02-27Add a FIXME about the VECTOR_SHUFFLE evil hack.Duncan Sands
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47676 91177308-0d34-0410-b5e6-96231b3b80d8
2008-02-27LegalizeTypes support for EXTRACT_VECTOR_ELT. TheDuncan Sands
approach taken is different to that in LegalizeDAG when it is a question of expanding or promoting the result type: for example, if extracting an i64 from a <2 x i64>, when i64 needs expanding, it bitcasts the vector to <4 x i32>, extracts the appropriate two i32's, and uses those for the Lo and Hi parts. Likewise, when extracting an i16 from a <4 x i16>, and i16 needs promoting, it bitcasts the vector to <2 x i32>, extracts the appropriate i32, twiddles the bits if necessary, and uses that as the promoted value. This puts more pressure on bitcast legalization, and I've added the appropriate cases. They needed to be added anyway since users can generate such bitcasts too if they want to. Also, when considering various cases (Legal, Promote, Expand, Scalarize, Split) it is a pain that expand can correspond to Expand, Scalarize or Split, so I've changed the LegalizeTypes enum so it lists those different cases - now Expand only means splitting a scalar in two. The code produced is the same as by LegalizeDAG for all relevant testcases, except for 2007-10-31-extractelement-i64.ll, where the code seems to have improved (see below; can an expert please tell me if it is better or not). Before < vs after >. < subl $92, %esp < movaps %xmm0, 64(%esp) < movaps %xmm0, (%esp) < movl 4(%esp), %eax < movl %eax, 28(%esp) < movl (%esp), %eax < movl %eax, 24(%esp) < movq 24(%esp), %mm0 < movq %mm0, 56(%esp) --- > subl $44, %esp > movaps %xmm0, 16(%esp) > pshufd $1, %xmm0, %xmm1 > movd %xmm1, 4(%esp) > movd %xmm0, (%esp) > movq (%esp), %mm0 > movq %mm0, 8(%esp) < subl $92, %esp < movaps %xmm0, 64(%esp) < movaps %xmm0, (%esp) < movl 12(%esp), %eax < movl %eax, 28(%esp) < movl 8(%esp), %eax < movl %eax, 24(%esp) < movq 24(%esp), %mm0 < movq %mm0, 56(%esp) --- > subl $44, %esp > movaps %xmm0, 16(%esp) > pshufd $3, %xmm0, %xmm1 > movd %xmm1, 4(%esp) > movhlps %xmm0, %xmm0 > movd %xmm0, (%esp) > movq (%esp), %mm0 > movq %mm0, 8(%esp) < subl $92, %esp < movaps %xmm0, 64(%esp) --- > subl $44, %esp < movl 16(%esp), %eax < movl %eax, 48(%esp) < movl 20(%esp), %eax < movl %eax, 52(%esp) < movaps %xmm0, (%esp) < movl 4(%esp), %eax < movl %eax, 60(%esp) < movl (%esp), %eax < movl %eax, 56(%esp) --- > pshufd $1, %xmm0, %xmm1 > movd %xmm1, 4(%esp) > movd %xmm0, (%esp) > movd %xmm1, 12(%esp) > movd %xmm0, 8(%esp) < subl $92, %esp < movaps %xmm0, 64(%esp) --- > subl $44, %esp < movl 24(%esp), %eax < movl %eax, 48(%esp) < movl 28(%esp), %eax < movl %eax, 52(%esp) < movaps %xmm0, (%esp) < movl 12(%esp), %eax < movl %eax, 60(%esp) < movl 8(%esp), %eax < movl %eax, 56(%esp) --- > pshufd $3, %xmm0, %xmm1 > movd %xmm1, 4(%esp) > movhlps %xmm0, %xmm0 > movd %xmm0, (%esp) > movd %xmm1, 12(%esp) > movd %xmm0, 8(%esp) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47672 91177308-0d34-0410-b5e6-96231b3b80d8
2008-02-27LegalizeTypes support for legalizing the maskDuncan Sands
operand of a VECTOR_SHUFFLE. The mask is a vector of constant integers. The code in LegalizeDAG doesn't bother to legalize the mask, since it's basically just storage for a bunch of constants, however LegalizeTypes is more picky. The problem is that there may not exist any legal vector-of-integers type with a legal element type, so it is impossible to create a legal mask! Unless of course you cheat by creating a BUILD_VECTOR where the operands have a different type to the element type of the vector being built... This is pretty ugly but works - all relevant tests in the testsuite pass, and produce the same assembler with and without LegalizeTypes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47670 91177308-0d34-0410-b5e6-96231b3b80d8
2008-02-27LegalizeTypes support for INSERT_VECTOR_ELT.Duncan Sands
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47669 91177308-0d34-0410-b5e6-96231b3b80d8
2008-02-27Don't track max alignment during stack object allocations since they can be ↵Evan Cheng
deleted later. Let PEI compute it. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47668 91177308-0d34-0410-b5e6-96231b3b80d8
2008-02-27Support for legalizing MEMBARRIER.Duncan Sands
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47667 91177308-0d34-0410-b5e6-96231b3b80d8
2008-02-27Final de-tabification.Bill Wendling
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47663 91177308-0d34-0410-b5e6-96231b3b80d8
2008-02-27Spiller now remove unused spill slots.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47657 91177308-0d34-0410-b5e6-96231b3b80d8
2008-02-27Teach Legalize how to expand an EXTRACT_ELEMENT.Dan Gohman
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47656 91177308-0d34-0410-b5e6-96231b3b80d8
2008-02-27Convert the last remaining users of the non-APInt form ofDan Gohman
ComputeMaskedBits to use the APInt form, and remove the non-APInt form. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47654 91177308-0d34-0410-b5e6-96231b3b80d8
2008-02-27Convert SimplifyDemandedMask and ShrinkDemandedConstant to use APInt.Dan Gohman
Change several cases in SimplifyDemandedMask that don't ever do any simplifying to reuse the logic in ComputeMaskedBits instead of duplicating it. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47648 91177308-0d34-0410-b5e6-96231b3b80d8
2008-02-26Use a smallvector for inactiveCounts and initialize it lazily Chris Lattner
instead of init'ing it maximally to zeros on entry. getFreePhysReg is pretty hot and only a few elements are typically used. This speeds up linscan by 5% on 176.gcc. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47631 91177308-0d34-0410-b5e6-96231b3b80d8
2008-02-26Rename PrintableName to Name.Bill Wendling
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47629 91177308-0d34-0410-b5e6-96231b3b80d8
2008-02-26Change "Name" to "AsmName" in the target register info. Gee, a refactoring toolBill Wendling
would have been a Godsend here! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47625 91177308-0d34-0410-b5e6-96231b3b80d8
2008-02-26Enable -coalescer-commute-instrs by default.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47623 91177308-0d34-0410-b5e6-96231b3b80d8
2008-02-26Avoid aborting on invalid shift counts.Dan Gohman
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47612 91177308-0d34-0410-b5e6-96231b3b80d8
2008-02-26Fix PR2096, a regression introduced with my patch last night. ThisChris Lattner
also fixes cfrac, flops, and 175.vpr git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47605 91177308-0d34-0410-b5e6-96231b3b80d8
2008-02-26Fix a nasty bug in LegalizeTypes (spotted inDuncan Sands
CodeGen/PowerPC/illegal-element-type.ll): suppose a node X is processed, and processing maps it to a node Y. Then X continues to exist in the DAG, but with no users. While processing some other node, a new node may be created that happens to be equal to X, and thus X will be reused rather than a truly new node. This can cause X to "magically reappear", and since it is in the Processed state in will not be reprocessed, so at the end of type legalization the illegal node X can still be present. The solution is to replace X with Y whenever X gets resurrected like this. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47601 91177308-0d34-0410-b5e6-96231b3b80d8
2008-02-26De-tabify.Bill Wendling
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47598 91177308-0d34-0410-b5e6-96231b3b80d8
2008-02-26This is possible:Evan Cheng
vr1 = extract_subreg vr2, 3 ... vr3 = extract_subreg vr1, 2 The end result is vr3 is equal to vr2 with subidx 2. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47592 91177308-0d34-0410-b5e6-96231b3b80d8
2008-02-26Fix isNegatibleForFree to not return true for ConstantFP nodes Chris Lattner
after legalize. Just because a constant is legal (e.g. 0.0 in SSE) doesn't mean that its negated value is legal (-0.0). We could make this stronger by checking to see if the negated constant is actually legal post negation, but it doesn't seem like a big deal. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47591 91177308-0d34-0410-b5e6-96231b3b80d8
2008-02-26Refactor inline asm constraint matching code out of SDIsel into TargetLowering.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47587 91177308-0d34-0410-b5e6-96231b3b80d8
2008-02-25Make some static variables const.Dan Gohman
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47566 91177308-0d34-0410-b5e6-96231b3b80d8
2008-02-25Convert MaskedValueIsZero and all its users to use APInt. Also addDan Gohman
a SignBitIsZero function to simplify a common use case. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47561 91177308-0d34-0410-b5e6-96231b3b80d8
2008-02-25All remat'ed loads cannot be folded into two-address code. Not just argument ↵Evan Cheng
loads. This change doesn't really have any impact on codegen. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47557 91177308-0d34-0410-b5e6-96231b3b80d8
2008-02-25In debug builds check that the key property holds: allDuncan Sands
result and operand types are legal. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47546 91177308-0d34-0410-b5e6-96231b3b80d8
2008-02-25Correctly determine whether a argument load can be folded into its uses.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47545 91177308-0d34-0410-b5e6-96231b3b80d8
2008-02-24Add support to LegalizeTypes for building legal vectorsDuncan Sands
out of illegal elements (BUILD_VECTOR). Uses and beefs up BUILD_PAIR, though it didn't really have to. Like most of LegalizeTypes, does not support soft-float. This cures all "make check" vector building failures. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47537 91177308-0d34-0410-b5e6-96231b3b80d8
2008-02-24Some platforms use the same name for 32-bit and 64-bit registers (likeBill Wendling
%r3 on PPC) in their ASM files. However, it's hard for humans to read during debugging. Adding a new field to the register data that lets you specify a different name to be printed than the one that goes into the ASM file -- %x3 instead of %r3, for instance. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47534 91177308-0d34-0410-b5e6-96231b3b80d8
2008-02-23Rematerialization logic was overly conservative when it comes to loads from ↵Evan Cheng
fixed stack slots. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47529 91177308-0d34-0410-b5e6-96231b3b80d8
2008-02-23If remating a machine instr with virtual register operand, make sure the vr ↵Evan Cheng
is avaliable at all uses regardless of whether it would be folded. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47526 91177308-0d34-0410-b5e6-96231b3b80d8
2008-02-23Recognize loads of arguments as re-materializable first. Therefore if ↵Evan Cheng
isReallyTriviallyReMaterializable() returns true it doesn't confuse it as a "normal" re-materializable instruction. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47520 91177308-0d34-0410-b5e6-96231b3b80d8
2008-02-23Fix spill weight updating bug.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47507 91177308-0d34-0410-b5e6-96231b3b80d8
2008-02-22Same isPhysRegAvailable bug as local register allocator.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47500 91177308-0d34-0410-b5e6-96231b3b80d8
2008-02-22Really really bad local register allocator bug. On X86, it was never using ↵Evan Cheng
ESI, EDI, and EBP because of a bug in RALocal::isPhysRegAvailable(). For example, when it checks if ESI is available, it then looks at registers aliases to ESI. SIL is marked -2 (not allocatable) but isPhysRegAvailable() incorrectly assumes it is in use and returns false for ESI. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47499 91177308-0d34-0410-b5e6-96231b3b80d8
2008-02-22Add debugging printfs.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47496 91177308-0d34-0410-b5e6-96231b3b80d8
2008-02-22Make sure reload of implicit uses are issued before remat's.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47492 91177308-0d34-0410-b5e6-96231b3b80d8
2008-02-22Pass alignment on ByVal parameters, from FE, allDale Johannesen
the way through. It is now used for codegen. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47484 91177308-0d34-0410-b5e6-96231b3b80d8
2008-02-22Enable re-materialization of instructions which have virtual register ↵Evan Cheng
operands if the definition of the operand also reaches its uses. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47475 91177308-0d34-0410-b5e6-96231b3b80d8
2008-02-22Fix compiler warning.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47468 91177308-0d34-0410-b5e6-96231b3b80d8
2008-02-22Fix a regression in 403.gcc and 186.crafty introduced in 47383. To testDan Gohman
that a value is >= 32, check that all of the high bits are zero, not just one or more. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47467 91177308-0d34-0410-b5e6-96231b3b80d8
2008-02-21Make the clobber analysis a bit more smart: we only are careful about Chris Lattner
early clobbers if the clobber list contains a *register* not some thing like {memory}, {dirflag} etc. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47457 91177308-0d34-0410-b5e6-96231b3b80d8
2008-02-21Treat clobber operands like early clobbers: if we haveChris Lattner
any, we force sdisel to do all regalloc for an asm. This leads to gross but correct codegen. This fixes the rest of PR2078. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47454 91177308-0d34-0410-b5e6-96231b3b80d8
2008-02-21Clear PhysRegPartUse for the sub register as well.Bill Wendling
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47453 91177308-0d34-0410-b5e6-96231b3b80d8
2008-02-21Adjust the MaxAlignment for the special register scavenging spill slot.Bill Wendling
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47452 91177308-0d34-0410-b5e6-96231b3b80d8
2008-02-21Help testing.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47448 91177308-0d34-0410-b5e6-96231b3b80d8
2008-02-21Better names as per Evan's requestAndrew Lenharth
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47435 91177308-0d34-0410-b5e6-96231b3b80d8
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