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AgeCommit message (Expand)Author
2012-03-22Source order scheduler should not preschedule nodes with multiple uses. rdar:...Evan Cheng
2012-03-22Assign node orders to target intrinsics which do not produce results. rdar://...Evan Cheng
2012-03-22In erroneous inline assembly we could mistakenly try to access theEric Christopher
2012-03-22[fast-isel] Fold "urem x, pow2" -> "and x, pow2-1". This should fix the 271%Chad Rosier
2012-03-21Checking a build_vector for an all-ones value.Jim Grosbach
2012-03-21misched: fix LiveInterval update for bottom-up schedulingAndrew Trick
2012-03-21misched: trace LiveIntervals after scheduling.Andrew Trick
2012-03-21misched: obvious iterator update fixes for bottom-up.Andrew Trick
2012-03-21misched: cleanup main loopAndrew Trick
2012-03-21misched: fix LI update for bottom-up.Andrew Trick
2012-03-20It's possible to have a constant expression who's size is quite big (e.g.,Bill Wendling
2012-03-20When combining (vextract shuffle (load ), <1,u,u,u>), 0) -> (load ), add user...Craig Topper
2012-03-20Do everything up to generating code to try to get a register forEric Christopher
2012-03-20Untabify.Eric Christopher
2012-03-20Add another debugging statement here.Eric Christopher
2012-03-20Use lookUpRegForValue here instead of duplicating the code.Eric Christopher
2012-03-19f16 FDIV can now be legalized by promoting to f32Pete Cooper
2012-03-19Add an option to the MI scheduler to cut off scheduling after a fixed number ofLang Hames
2012-03-19Fix DAG combine which creates illegal vector shuffles. Patch by Heikki Kultala.Duncan Sands
2012-03-17CriticalAntiDepBreaker: Replace a SmallSet of regs with a much denser BitVector.Benjamin Kramer
2012-03-17MachineInstr: Inline the fast path (non-bundle instruction) of hasProperty.Benjamin Kramer
2012-03-16ScheduleDAGInstrs: When adding uses we add them into a set that's empty at th...Benjamin Kramer
2012-03-16Limit the number of memory operands in MachineInstr to 2^16 and store the num...Benjamin Kramer
2012-03-16CriticalAntiDepBreaker: BasicBlock::size is an expensive operation, reuse the...Benjamin Kramer
2012-03-16misched: add DAG edges from vreg defs to ExitSU.Andrew Trick
2012-03-16Revert r152705, which reapplied r152486 as this appears to be causing failuresChad Rosier
2012-03-16Revert r152613 (and r152614), "Inline the d'tor and add an anchor instead." f...NAKAMURA Takumi
2012-03-15For types with a parent of the compile unit make sure and emitEric Christopher
2012-03-15We actually handle AllocaInst via getRegForValue below just fine.Eric Christopher
2012-03-15Add some debugging output into fast isel as well.Eric Christopher
2012-03-15Add another debug statement.Eric Christopher
2012-03-15Tabs.Eric Christopher
2012-03-15Typo.Eric Christopher
2012-03-15When optimizing certain BUILD_VECTOR nodes into other BUILD_VECTOR nodes, add...Nadav Rotem
2012-03-15Revert the removal of DW_AT_MIPS_linkage_name when we aren't puttingEric Christopher
2012-03-15Add a xform to the DAG combiner.Bill Wendling
2012-03-14Silence operator precedence warnings.Benjamin Kramer
2012-03-14Reapply r152486 with a fix for the nightly testers.Bill Wendling
2012-03-14Insert the debugging instructions in one fell-swoop so that it doesn't call theBill Wendling
2012-03-14misched: implemented a framework for top-down or bottom-up scheduling.Andrew Trick
2012-03-14misched commentsAndrew Trick
2012-03-14Remove the DW_AT_MIPS_linkage name attribute when we don't need itEric Christopher
2012-03-13Fortify r152675 a bit. Although I'm not able to come up with a test case that...Evan Cheng
2012-03-13DAG combine incorrectly optimize (i32 vextract (v4i16 load $addr), c) toEvan Cheng
2012-03-13s/SjLjEHPass/SjLjEHPrepare/Bill Wendling
2012-03-13Add a return type.Bill Wendling
2012-03-13Inline the d'tor and add an anchor instead.Bill Wendling
2012-03-13Refactor the SelectionDAG's 'dump' methods into their own .cpp file.Bill Wendling
2012-03-13Fixed typo in comment.Lang Hames
2012-03-12Revert due to nightly test failures.Bill Wendling