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2013-04-01Merge load/store sequences with adresses: base + index + offsetArnold Schwaighofer
We would also like to merge sequences that involve a variable index like in the example below. int index = *idx++ int i0 = c[index+0]; int i1 = c[index+1]; b[0] = i0; b[1] = i1; By extending the parsing of the base pointer to handle dags that contain a base, index, and offset we can handle examples like the one above. The dag for the code above will look something like: (load (i64 add (i64 copyfromreg %c) (i64 signextend (i8 load %index)))) (load (i64 add (i64 copyfromreg %c) (i64 signextend (i32 add (i32 signextend (i8 load %index)) (i32 1))))) The code that parses the tree ignores the intermediate sign extensions. However, if there is a sign extension it needs to be on all indexes. (load (i64 add (i64 copyfromreg %c) (i64 signextend (add (i8 load %index) (i8 1)))) vs (load (i64 add (i64 copyfromreg %c) (i64 signextend (i32 add (i32 signextend (i8 load %index)) (i32 1))))) radar://13536387 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178483 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-30DAGCombine: visitXOR can replace a node without returning it, bail out in ↵Benjamin Kramer
that case. Fixes the crash reported in PR15608. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178429 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-29Use SmallVectorImpl instead of SmallVector at the uses.Eric Christopher
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178386 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-29Use 12 as the magic number for our abbreviation data and ourEric Christopher
die values. A lot of DIEs have 10 attributes in C++ code (example clang), none had more than 12. Seems like a good default. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178366 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-29Move the construction of the skeleton compile unit after theEric Christopher
entire original compile unit has been constructed. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178365 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-29Remove the old CodePlacementOpt pass.Benjamin Kramer
It was superseded by MachineBlockPlacement and disabled by default since LLVM 3.1. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178349 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-29Fix a typoNadav Rotem
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178346 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-28[fast-isel] Add a preemptive fix for the case where we fail to materialize anChad Rosier
immediate in a register. I don't believe this should ever fail, but I see no harm in trying to make this code bullet proof. I've added an assert to ensure my assumtion is correct. If the assertion fires something is wrong and we should fix it, rather then just silently fall back to SelectionDAG isel. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178305 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-27Fix target-customized spilling in the register scavengerHal Finkel
This is a follow-up to r178073 (which should actually make target-customized spilling work again). I still don't have a regression test for this (but it would be good to have one; Thumb 1 and Mips16 use this callback as well). Patch by Richard Sandiford. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178137 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-26Fix the register scavenger for targets that provide custom spillingHal Finkel
As pointed out by Richard Sandiford, my recent updates to the register scavenger broke targets that use custom spilling (because the new code assumed that if there were no valid spill slots, than spilling would be impossible). I don't have a test case, but it should be possible to create one for Thumb 1, Mips 16, etc. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178073 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-26Update PEI's virtual-register-based scavenging to support multiple ↵Hal Finkel
simultaneous mappings The previous algorithm could not deal properly with scavenging multiple virtual registers because it kept only one live virtual -> physical mapping (and iterated through operands in order). Now we don't maintain a current mapping, but rather use replaceRegWith to completely remove the virtual register as soon as the mapping is established. In order to allow the register scavenger to return a physical register killed by an instruction for definition by that same instruction, we now call RS->forward(I) prior to eliminating virtual registers defined in I. This requires a minor update to forward to ignore virtual registers. These new features will be tested in forthcoming commits. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178058 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-25Enhance folding of (extract_subvec (insert_subvec V1, V2, IIdx), EIdx)Michael Liao
- Handle the case where the result of 'insert_subvect' is bitcasted before 'extract_subvec'. This removes the redundant insertf128/extractf128 pair on unaligned 256-bit vector load/store on vectors of non 64-bit integer. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177945 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-25Disable some unsafe-fp-math DAG-combine transformation after legalization.Shuxin Yang
For instance, following transformation will be disabled: x + x + x => 3.0f * x; The problem of these transformations is that it introduces a FP constant, which following Instruction-Selection pass cannot handle. Reviewed by Nadav, thanks a lot! rdar://13445387 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177933 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-25Couple more sets of tidying.Eric Christopher
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177920 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-25Formatting.Eric Christopher
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177898 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-25Teach cmake about the new Erlang GC files.Duncan Sands
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177869 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-25Add a GC plugin for ErlangYiannis Tsiouris
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177867 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-23Remove the type legality check from the SelectionDAGBuilder when it lowers ↵Owen Anderson
@llvm.fmuladd to ISD::FMA nodes. Performing this check unilaterally prevented us from generating FMAs when the incoming IR contained illegal vector types which would eventually be legalized to underlying types that *did* support FMA. For example, an @llvm.fmuladd on an OpenCL float16 should become a sequence of float4 FMAs, not float4 fmul+fadd's. NOTE: Because we still call the target-specific profitability hook, individual targets can reinstate the old behavior, if desired, by simply performing the legality check inside their callback hook. They can also perform more sophisticated legality checks, if, for example, some illegal vector types can be productively implemented as FMAs, but not others. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177820 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-23Fix comparison of mixed signednessHal Finkel
177774 broke the lld-x86_64-darwin11 builder; error: error: comparison of integers of different signs: 'int' and 'size_type' (aka 'unsigned long') for (SI = 0; SI < Scavenged.size(); ++SI) ~~ ^ ~~~~~~~~~~~~~~~~ Fix this by making SI also unsigned. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177780 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-22Allow the register scavenger to spill multiple registersHal Finkel
This patch lets the register scavenger make use of multiple spill slots in order to guarantee that it will be able to provide multiple registers simultaneously. To support this, the RS's API has changed slightly: setScavengingFrameIndex / getScavengingFrameIndex have been replaced by addScavengingFrameIndex / isScavengingFrameIndex / getScavengingFrameIndices. In forthcoming commits, the PowerPC backend will use this capability in order to implement the spilling of condition registers, and some special-purpose registers, without relying on r0 being reserved. In some cases, spilling these registers requires two GPRs: one for addressing and one to hold the value being transferred. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177774 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-22Remove ScavengedRC from RegisterScavengingHal Finkel
ScavengedRC was a dead private variable (set, but not otherwise used). No functionality change intended. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177708 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-21Fix missing std::. Not sure how this compiles for anyone else.Matt Arsenault
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177620 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-20Make variable name more explicit and eliminate redundant lookup in ↵Justin Holewinski
SDNodeOrdering git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177600 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-20When computing the demanded bits of Load SDNodes, make sure that we are ↵Nadav Rotem
looking at the loaded-value operand and not the ptr result (in case of pre-inc loads). rdar://13348420 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177596 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-20Revert "pre-RA-sched: fix TargetOpcode usage"Christian Konig
This reverts commit 06091513c283c863296f01cc7c2e86b56bb50d02. The code is obviously wrong, but the trivial fix causes inefficient code generation on X86. Somebody with more knowledge of the code needs to take a look here. Signed-off-by: Christian König <christian.koenig@amd.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177529 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-20Move SDNode order propagation to SDNodeOrdering, which also fixes a missedJustin Holewinski
case of order propagation during isel. Thanks Owen for the suggestion! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177525 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-20pre-RA-sched: fix TargetOpcode usageChristian Konig
TargetOpcodes need to be treaded as Machine- and not ISD-Opcodes. Signed-off-by: Christian König <christian.koenig@amd.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177518 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-20Propagate DAG node ordering during type legalization and instruction selectionJustin Holewinski
A node's ordering is only propagated during legalization if (a) the new node does not have an ordering (is not a CSE'd node), or (b) the new node has an ordering that is higher than the node being legalized. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177465 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-18Move #include of BitVector from .h to .cpp file.Jakub Staszak
Also remove unneeded #include and forward declaration. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177357 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-18Add some constantness.Jakub Staszak
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177356 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-18Fix integer comparison in DIEInteger::BestForm.Hans Wennborg
The always-true "(int)Int == (signed)Int" comparison was found while experimenting with a potential new Clang warning. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177290 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-18Windows TLS: Section name prefix to ensure correct orderAnton Korobeynikov
The linker sorts the .tls$<xyz> sections by name, and we need to make sure any extra sections we produce (e.g. for weak globals) always end up between .tls$AAA and .tls$ZZZ, even if the name starts with e.g. an underscore. Patch by David Nadlinger! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177256 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-16Change the default latency for implicit defs.Andrew Trick
Implicit defs are not currently positional and not modeled by the per-operand machine model. Unfortunately, we treat defs that are part of the architectural instruction description, like flags, the same as other implicit defs. Really, they should have a fixed MachineInstr layout and probably shouldn't be "implicit" at all. For now, we'll change the default latency to be the max operand latency. That will give flag setting operands full latency for x86 folded loads. Other kinds of "fake" implicit defs don't occur prior to regalloc anyway, and we would like them to go away postRegAlloc as well. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177227 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-14Move estimateStackSize from ARM into MachineFrameInfoHal Finkel
This is a generic function (derived from PEI); moving it into MachineFrameInfo eliminates a current redundancy between the ARM and AArch64 backends, and will allow it to be used by the PowerPC target code. No functionality change intended. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177111 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-14Provide the register scavenger to processFunctionBeforeFrameFinalizedHal Finkel
Add the current PEI register scavenger as a parameter to the processFunctionBeforeFrameFinalized callback. This change is necessary in order to allow the PowerPC target code to set the register scavenger frame index after the save-area offset adjustments performed by processFunctionBeforeFrameFinalized. Only after these adjustments have been made is it possible to estimate the size of the stack frame. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177108 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-13Reset some of the target options which affect code generation.Bill Wendling
This doesn't reset all of the target options within the TargetOptions object. This is because some of those are ABI-specific and must be determined if it's okay to change those on the fly. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176986 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-13No functionality change. Use unreachable in getCUOffset.Manman Ren
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176963 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-13No functionality change. Use unreachable in getCompileUnit.Manman Ren
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176962 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-13Check register classes also when changing them.Jakob Stoklund Olesen
We have the same assertion in createVirtualRegister. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176959 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-12Debug Info: use DW_FORM_ref_addr instead of DW_FORM_ref4 if the referenced DIEManman Ren
belongs to a different compile unit. DW_FORM_ref_addr should be used for cross compile-unit reference. When compiling a large application, we got a dwarfdump verification error where abstract_origin points to nowhere. This error can't be reproduced on any testing case in MultiSource. We may have other cases where we use DW_FORM_ref4 unconditionally. rdar://problem/13370501 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176882 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-12Avoid generating ISD::SELECT for vector operands to SIGN_EXTENDRichard Relph
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176881 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-11Remove support for versioned debug info.David Blaikie
Versioned debug info support has been a burden to maintain & also compromised current debug info verification by causing test cases testing old debug info to remain rather than being updated to the latest. It also makes it hard to add or change the metadata schema by requiring various backwards-compatibility in the DI* hierarchy. So it's being removed in preparation for new changes to the schema to tidy up old/unnecessary fields and add new fields needed for new debug info (well, new to LLVM at least). The more surprising part of this is the changes to DI*::Verify - this became necessary due to the changes to AsmWriter. AsmWriter was relying on the version test to decide which bits of metadata were actually debug info when printing the comment annotations. Without the version information the tag numbers were too common & it would print debug info on random metadata that happened to start with an integer that matched a tag number. Instead this change makes the Verify functions more precise (just adding "number of operands" checks - not type checking those operands yet) & relies on that to decide which metadata is debug info metadata. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176838 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-11Fix a crasher newly introduced in r176659/r176649, where fast-isel tries toNick Lewycky
lower an expect intrinsic that is a constant expression. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176830 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-10Cleanup #includes.Jakub Staszak
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176787 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-08Remove wrong and unnecessary assertion.Jakob Stoklund Olesen
PHIs are allowed to have multiple operand pairs per predecessor, and this code works just fine when it happens. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176734 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-08Disable statistics on Release builds and move tests that depend on -stats.Jan Wen Voung
Summary: Statistics are still available in Release+Asserts (any +Asserts builds), and stats can also be turned on with LLVM_ENABLE_STATS. Move some of the FastISel stats that were moved under DEBUG() back out of DEBUG(), since stats are disabled across the board now. Many tests depend on grepping "-stats" output. Move those into a orig_dir/Stats/. so that they can be marked as unsupported when building without statistics. Differential Revision: http://llvm-reviews.chandlerc.com/D486 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176733 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-08Rewrite the physreg part of findLastUseBefore().Jakob Stoklund Olesen
To find the last use of a register unit, start from the bottom and scan upwards until a user is found. <rdar://problem/13353090> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176706 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-08Remove default from fully covered switch.Benjamin Kramer
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176703 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-08LegalizeDAG: Respect the result of TLI.getBooleanContents() when expanding SETCCTom Stellard
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176695 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-08DAGCombiner: Use correct value type for checking legality of BR_CC v3Tom Stellard
LegalizeDAG.cpp uses the value of the comparison operands when checking the legality of BR_CC, so DAGCombiner should do the same. v2: - Expand more BR_CC value types for NVPTX v3: - Expand correct BR_CC value types for Hexagon, Mips, and XCore. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176694 91177308-0d34-0410-b5e6-96231b3b80d8
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