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2012-11-14Handle DAG CSE adding new uses during ReplaceAllUsesWith. Fixes PR14333.Rafael Espindola
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167912 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-14Use TARGET2 relocation for TType references on ARM.Anton Korobeynikov
Do some cleanup of the code while here. Inspired by patch by Logan Chien! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167904 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-13Revert "Use the 'count' attribute instead of the 'upper_bound' attribute."Eric Christopher
temporarily as it is breaking the gdb bots. This reverts commit r167806/e7ff4c14b157746b3e0228d2dce9f70712d1c126. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167886 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-13Revert -join-splitedges to a boolean cmd line option.Andrew Trick
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167880 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-13The MachineScheduler does not currently require JoinSplitEdges.Andrew Trick
This option will eventually either be enabled unconditionally or replaced by a more general live range splitting optimization. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167879 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-13[MC][COFF] Emit weak symbols to the correct section. Patch by Dmitry Puzirev!Michael J. Spencer
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167877 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-13Do not consider a machine instruction that uses and defines the sameUlrich Weigand
physical register as candidate for common subexpression elimination in MachineCSE. This fixes a bug on PowerPC in MultiSource/Applications/oggenc/oggenc caused by MachineCSE invalidly merging two separate DYNALLOC insns. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167855 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-13Fix -join-splitedges: my previous "cleanup" broke it.Andrew Trick
Working on reducing unit tests. This won't be enabled unless a subtarget enables misched. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167851 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-13Codegen support for arbitrary vector getelementptrs.Duncan Sands
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167830 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-13misched: Allow subtargets to enable misched and dependent options.Andrew Trick
This allows me to begin enabling (or backing out) misched by default for one subtarget at a time. To run misched we typically want to: - Disable SelectionDAG scheduling (use the source order scheduler) - Enable more aggressive coalescing (until we decide to always run the coalescer this way) - Enable MachineScheduler pass itself. Disabling PostRA sched may follow for some subtargets. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167826 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-13Added RegisterCoalescer support for joining global copies first.Andrew Trick
This adds the -join-globalcopies option which can be enabled by default once misched is also enabled. Ideally, the register coalescer would be able to split local live ranges in a way that produces copies that can be easily resolved by the scheduler. Until then, this heuristic should be good enough to at least allow the scheduler to run after coalescing. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167825 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-13misched: Don't consider artificial edges weak edges.Andrew Trick
For now be more conservative in case other out-of-tree schedulers rely on the old behavior of artificial edges. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167808 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-13Use the 'count' attribute instead of the 'upper_bound' attribute.Bill Wendling
If we have a type 'int a[1]' and a type 'int b[0]', the generated DWARF is the same for both of them because we use the 'upper_bound' attribute. Instead use the 'count' attrbute, which gives the correct number of elements in the array. <rdar://problem/12566646> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167806 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-13Cleanup the main RegisterCoalescer loop.Andrew Trick
Block priorities still apply outside loops. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167793 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-12Cleanup -join-splitedges. Make the loop more obvious.Andrew Trick
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167785 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-12Add an option to enable prototype "fission" capabilities and debug changes.Eric Christopher
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167765 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-12Added a temporary option to avoid critical edges splitting.Andrew Trick
This teaches the register coalescer to be less prone to split critical edges. I am currently benchmarking this with the new (post-coalescer) scheduler. I plan to enable this by default and remove the option as soon as misched is enabled. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167758 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-12misched: rename interfaceto avoid gcc warningsAndrew Trick
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167753 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-12misched: Target-independent support for MacroFusion.Andrew Trick
Uses the infrastructure from r167742 to support clustering instructure that the target processor can "fuse". e.g. cmp+jmp. Next step: target hook implementations with test cases, and enable. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167744 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-12misched: Target-independent support for load/store clustering.Andrew Trick
This infrastructure is generally useful for any target that wants to strongly prefer two instructions to be adjacent after scheduling. A following checkin will add target-specific hooks with unit tests. Then this feature will be enabled by default with misched. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167742 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-12misched: Infrastructure for weak DAG edges.Andrew Trick
This adds support for weak DAG edges to the general scheduling infrastructure in preparation for MachineScheduler support for heuristics based on weak edges. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167738 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-09Fix assertions in updateRegMaskSlots().Jakob Stoklund Olesen
The RegMaskSlots contains 'r' slots while NewIdx and OldIdx are 'B' slots. This broke the checks in the assertions. This fixes PR14302. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167625 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-09Silence GCC warning about falling off the end of a non-void function.Benjamin Kramer
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167618 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-07misched: Heuristics based on the machine model.Andrew Trick
misched is disabled by default. With -enable-misched, these heuristics balance the schedule to simultaneously avoid saturating processor resources, expose ILP, and minimize register pressure. I've been analyzing the performance of these heuristics on everything in the llvm test suite in addition to a few other benchmarks. I would like each heuristic check to be verified by a unit test, but I'm still trying to figure out the best way to do that. The heuristics are still in considerable flux, but as they are refined we should be rigorous about unit testing the improvements. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167527 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-07misched: handle on-the-fly regpressure queries better for 2-addrAndrew Trick
instructions without relying on liveintervals. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167526 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-07Add comment describing what's going on here.Bill Wendling
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167525 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-07When we're updating the subprogram scope DIE, we want to determine if we'reBill Wendling
updating an abstract DIE or not. If we are, then we use that. Its children will be added on later, as well as the object pointer attribute. Otherwise, this function may be called with a concrete DIE twice and adding the children and object pointer attribute to it twice. <rdar://problem/12401423&12600340> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167524 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-06[regallocfast] Make sure the MachineRegisterInfo is aware of clobbers from aChad Rosier
register masks. This is an obvious and necessary fix for a soon to be committed patch. No test case possible at this time. Reviewed by Jakob. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167498 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-06misched: TargetSchedule interface for machine resources.Andrew Trick
Expose the processor resources defined by the machine model to the scheduler and other clients through the TargetSchedule interface. Normalize each resource count with respect to other kinds of resources. This allows scheduling heuristics to balance resources against other kinds of resources and latency. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167444 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-06misched: Rename RemainingCount to avoid confusion with remaining resources.Andrew Trick
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167443 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-06ScheduleDAG interface. Added OrderKind to distinguish nonregister dependencies.Andrew Trick
This is in preparation for adding "weak" DAG edges, but generally simplifies the design. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167435 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-03Be careful not to optimize a SELECT_CC into a SETCC post-legalization if the ↵Owen Anderson
SETCC node would be illegal. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167344 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-01OutputArg: added an index of the original argument to match the change toManman Ren
InputArg in r165616. This will enable us to get the actual type for both InputArg and OutputArg. rdar://9932559 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167265 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-01Revert the majority of the next patch in the address space series:Chandler Carruth
r165941: Resubmit the changes to llvm core to update the functions to support different pointer sizes on a per address space basis. Despite this commit log, this change primarily changed stuff outside of VMCore, and those changes do not carry any tests for correctness (or even plausibility), and we have consistently found questionable or flat out incorrect cases in these changes. Most of them are probably correct, but we need to devise a system that makes it more clear when we have handled the address space concerns correctly, and ideally each pass that gets updated would receive an accompanying test case that exercises that pass specificaly w.r.t. alternate address spaces. However, from this commit, I have retained the new C API entry points. Those were an orthogonal change that probably should have been split apart, but they seem entirely good. In several places the changes were very obvious cleanups with no actual multiple address space code added; these I have not reverted when I spotted them. In a few other places there were merge conflicts due to a cleaner solution being implemented later, often not using address spaces at all. In those cases, I've preserved the new code which isn't address space dependent. This is part of my ongoing effort to clean out the partial address space code which carries high risk and low test coverage, and not likely to be finished before the 3.2 release looms closer. Duncan and I would both like to see the above issues addressed before we return to these changes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167222 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-01Revert the series of commits starting with r166578 which introduced theChandler Carruth
getIntPtrType support for multiple address spaces via a pointer type, and also introduced a crasher bug in the constant folder reported in PR14233. These commits also contained several problems that should really be addressed before they are re-committed. I have avoided reverting various cleanups to the DataLayout APIs that are reasonable to have moving forward in order to reduce the amount of churn, and minimize the number of commits that were reverted. I've also manually updated merge conflicts and manually arranged for the getIntPtrType function to stay in DataLayout and to be defined in a plausible way after this revert. Thanks to Duncan for working through this exact strategy with me, and Nick Lewycky for tracking down the really annoying crasher this triggered. (Test case to follow in its own commit.) After discussing with Duncan extensively, and based on a note from Micah, I'm going to continue to back out some more of the more problematic patches in this series in order to ensure we go into the LLVM 3.2 branch with a reasonable story here. I'll send a note to llvmdev explaining what's going on and why. Summary of reverted revisions: r166634: Fix a compiler warning with an unused variable. r166607: Add some cleanup to the DataLayout changes requested by Chandler. r166596: Revert "Back out r166591, not sure why this made it through since I cancelled the command. Bleh, sorry about this! r166591: Delete a directory that wasn't supposed to be checked in yet. r166578: Add in support for getIntPtrType to get the pointer type based on the address space. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167221 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-01Add a few more simple fast-math constant propagations and cancellations.Owen Anderson
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167200 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-01Exploit the new identity composition in composeSubRegIndices().Jakob Stoklund Olesen
The static compose() function in RegisterCoalescer was doing the exact same thing. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167198 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-31Replace some instances of UniqueVector with SetVector, which is slightly ↵Benjamin Kramer
cheaper. No functionality change. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167116 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-31Change signature of function RAFast::spillAll to avoid conversion betweenAkira Hatanaka
type MachineInstr* and MachineBasicBlock::iterator. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167088 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-31Check that iterator I is not the end iterator.Akira Hatanaka
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167086 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-30[inline asm] Get the mayLoad/mayStore directly from the MIOp_ExtraInfo operand.Chad Rosier
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167050 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-30Add a comment for r167040.Chad Rosier
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167046 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-30[inline asm] Implement mayLoad and mayStore for inline assembly. In general,Chad Rosier
the MachineInstr MayLoad/MayLoad flags are based on the tablegen implementation. For inline assembly, however, we need to compute these based on the constraints. Revert r166929 as this is no longer needed, but leave the test case in place. rdar://12033048 and PR13504 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167040 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-30Fix grammar.Bill Wendling
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167029 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-29In various places throughout the code generator, there were specialUlrich Weigand
checks to avoid performing compile-time arithmetic on PPCDoubleDouble. Now that APFloat supports arithmetic on PPCDoubleDouble, those checks are no longer needed, and we can treat the type like any other. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166958 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-29Completely disallow partial copies in adjustCopiesBackFrom().Jakob Stoklund Olesen
Partial copies can show up even when CoalescerPair.isPartial() returns false. For example: %vreg24:dsub_0<def> = COPY %vreg31:dsub_0; QPR:%vreg24,%vreg31 Such a partial-partial copy is not good enough for the transformation adjustCopiesBackFrom() needs to do. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166944 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-29Remove a wrapper around getIntPtrType added to GVN by Hal in commit 166624 (theDuncan Sands
wrapper returns a vector of integers when passed a vector of pointers) by having getIntPtrType itself return a vector of integers in this case. Outside of this wrapper, I didn't find anywhere in the codebase that was relying on the old behaviour for vectors of pointers, so give this a whirl through the buildbots. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166939 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-29This patch addresses a problem with the Post RA scheduler generating anPreston Gurd
incorrect instruction sequence due to it not being aware that an inline assembly instruction may reference memory. This patch fixes the problem by causing the scheduler to always assume that any inline assembly code instruction could access memory. This is necessary because the internal representation of the inline instruction does not include any information about memory accesses. This should fix PR13504. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166929 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-29Remove unused typedef.Lang Hames
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166910 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-27Never attempt to join an early-clobber def with a regular kill.Jakob Stoklund Olesen
This fixes PR14194. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166880 91177308-0d34-0410-b5e6-96231b3b80d8
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