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$ svn merge -c 114220 https://llvm.org/svn/llvm-project/llvm/trunk
--- Merging r114220 into '.':
U lib/CodeGen/MachineCSE.cpp
$ svn merge -c 114222 https://llvm.org/svn/llvm-project/llvm/trunk
--- Merging r114222 into '.':
G lib/CodeGen/MachineCSE.cpp
git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_28@114224 91177308-0d34-0410-b5e6-96231b3b80d8
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--- Merging r113848 into '.':
U lib/CodeGen/PeepholeOptimizer.cpp
must not peephole away side effects
git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_28@113913 91177308-0d34-0410-b5e6-96231b3b80d8
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$ svn merge -c 113299 https://llvm.org/svn/llvm-project/llvm/trunk
--- Merging r113299 into '.':
U lib/CodeGen/VirtRegRewriter.cpp
git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_28@113531 91177308-0d34-0410-b5e6-96231b3b80d8
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overload UserInInstr. Explicitly check Allocatable. The early exit in the
condition will mean the performance impact of the extra test should be
minimal.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113016 91177308-0d34-0410-b5e6-96231b3b80d8
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solve the root problem, but it corrects the bug in the code I added to
support legalizing in the case where the non-extended type is also legal.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112997 91177308-0d34-0410-b5e6-96231b3b80d8
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slot.
Teach it to also check for early clobbered aliases, and early clobber operands
following the current operand.
This fixes the miscompilation in PR8044 where EC registers eax and ecx were
being used for inputs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112988 91177308-0d34-0410-b5e6-96231b3b80d8
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Original commit message:
Use the SSAUpdator to turn calls to eh.exception that are not in a
landing pad into uses of registers rather than loads from a stack
slot. Doesn't touch the 'orrible hack code - Bill needs to persuade
me harder :)
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Thanks Chris!
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there are clearly no stores between the load and the store. This fixes
this miscompile reported as PR7833.
This breaks the test/CodeGen/X86/narrow_op-2.ll optimization, which is
safe, but awkward to prove safe. Move it to X86's README.txt.
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locally.
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intervals, and where the uses and defs of the original intervals were in the original code.
Spill intervals can be hidden using the "-rmf-intervals=virt-nospills*" option.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112809 91177308-0d34-0410-b5e6-96231b3b80d8
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at them since they'd end up in the register weights list. Tell it to stop
doing that.
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This caused a miscompilation in WebKit where %RAX had conflicting defs when
RemoveCopyByCommutingDef was commuting a %EAX use.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112751 91177308-0d34-0410-b5e6-96231b3b80d8
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physical register in a register class. Make sure to assert if the register
class is empty.
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PBQP version.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112742 91177308-0d34-0410-b5e6-96231b3b80d8
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r112728 did this for fast regalloc.
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self host errors on clang-x86-64.
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landing pad into uses of registers rather than loads from a stack
slot. Doesn't touch the 'orrible hack code - Bill needs to persuade
me harder :)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112702 91177308-0d34-0410-b5e6-96231b3b80d8
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This patch was developed on top of original patch by Artur Pietrek.
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Reserved registers are unpredictable, and are treated as always live by machine
DCE.
Allocatable registers are never reserved, and can be used for virtual registers.
Unreserved, unallocatable registers can not be used for virtual registers, but
otherwise behave like a normal allocatable register. Most targets only have
the flag register in this set.
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info to emit debug info.
Fixes Radar 8367011.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112623 91177308-0d34-0410-b5e6-96231b3b80d8
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1. Allocate them in the entry block of the function to enable function-wide
re-use. The instructions to create them should be re-materializable, so
there shouldn't be additional cost compared to creating them local
to the basic blocks where they are used.
2. Collect all of the frame index references for the function and sort them
by the local offset referenced. Iterate over the sorted list to
allocate the virtual base registers. This enables creation of base
registers optimized for positive-offset access of frame references.
(Note: This may be appropriate to later be a target hook to do the
sorting in a target appropriate manner. For now it's done here for
simplicity.)
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any more. I plan to reimplement alloca promotion using SSAUpdater later.
It looks like Bill's URoR logic really always needs domtree, so the pass
now always asks for domtree info.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112597 91177308-0d34-0410-b5e6-96231b3b80d8
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Eventually, we want to disable physreg coalescing completely, and let the
register allocator do its job using hints.
This option makes it possible to measure the impact of disabling physreg
coalescing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112567 91177308-0d34-0410-b5e6-96231b3b80d8
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1) nuke ConstDataCoalSection, which is dead.
2) revise my previous patch for rdar://8018335,
which was completely wrong. Specifically, it doesn't
make sense to mark __TEXT,__const_coal as PURE_INSTRUCTIONS,
because it is for readonly data. templates (it turns out)
go to const_coal_nt. The real fix for rdar://8018335 was
to give ConstTextCoalSection a section kind of ReadOnly
instead of Text.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112496 91177308-0d34-0410-b5e6-96231b3b80d8
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said (physical) register.
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instead of PromoteMemToReg. This allows it to stop using DF and DT,
eliminating a computation of DT and DF from clang -O3. Clang is now
down to 2 runs of DomFrontier.
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being actively maintained, improved, or extended.
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doesn't currently support dealing with this.
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