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fix, that is adequate while PR1508 remains unresolved.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37938 91177308-0d34-0410-b5e6-96231b3b80d8
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instead.
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endian swapping should be done, and update the code to use it. This fixes
some register ordering issues on big-endian systems, such as PowerPC,
introduced by the recent illegal by-val arguments changes.
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Almost all occurrences of "bytecode" in the sources have been eliminated.
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exception handling table if we encounter it multiple
times. Filters could be folded harder than this, but
that would mean a lot more work for not much gain.
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Drop the eh.filter intrinsic.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37875 91177308-0d34-0410-b5e6-96231b3b80d8
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follow the rules for undef used in instcombine.
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model to include f32 variants. Some factoring
improvments forthcoming.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37847 91177308-0d34-0410-b5e6-96231b3b80d8
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refactored getCopyFromParts and getCopyToParts, which are more general.
This effectively adds support for lowering illegal by-val vector call
arguments.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37843 91177308-0d34-0410-b5e6-96231b3b80d8
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visitFSUB to fold 0-B to -B in UnsafeFPMath mode. Also change visitFNEG
to use isNegatibleForFree/GetNegatedExpression instead of doing a subset
of the same thing manually.
This fixes test/CodeGen/X86/negative-sin.ll.
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Uncovered by _GLIBCXX_DEBUG.
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ordering and thus violated the strict weak ordering requirement of
priority_queue. Uncovered by _GLIBCXX_DEBUG.
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_GLIBCXX_DEBUG.
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vectors are split down to single elements as part of legalization.
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illegal value type will be transformed to, for code that needs the
register type after all transformations instead of just after the first
transformation.
Factor out the code that uses this information to do copy-from-regs and
copy-to-regs for various purposes into separate functions so that they
are done consistently.
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pad, add it as livein to all the blocks in the paths between the landing pad and the specified block.
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to compute the number and type of registers needed for vector values
instead of computing it manually. This fixes PR1529.
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with single-element vectors.
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the SPASS miscompilation)
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quality hit. will look at this soon.
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some issues)
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are read by later instructions.
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and code quality by ~2% on my tests.
A big thank you to Roman Levenstein for this patch! See
http://lists.cs.uiuc.edu/pipermail/llvm-commits/Week-of-Mon-20070618/050717.html
for more details.
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extended vector types. Remove the special SDNode opcodes used for pre-legalize
vector operations, and the special MVT::Vector type used with them. Adjust
lowering and legalize to work with the normal SDNode kinds instead, and to
use the normal MVT functions to work with vector types instead of using the
two special operands that the pre-legalize nodes held.
This allows pre-legalize and post-legalize DAGs, and the code that operates
on them, to be more consistent. Pre-legalize vector operators can be handled
more consistently with scalar operators. And, -view-dag-combine1-dags and
-view-legalize-dags now look prettier for vector code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37719 91177308-0d34-0410-b5e6-96231b3b80d8
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TargetLowering to SelectionDAG so that they have more convenient
access to the current DAG, in preparation for the ValueType routines
being changed from standalone functions to members of SelectionDAG for
the pre-legalize vector type changes.
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time. For Duraid's example. The overall isel time is reduced from 0.6255 sec to 0.1876 sec.
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TargetLowering::getNumRegisters and similar, to avoid confusion with
the actual number of elements for vector types.
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(add (select cc, 0, c), x) -> (select cc, x, (add, x, c))
(sub x, (select cc, 0, c)) -> (select cc, x, (sub, x, c))
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fallthrough unless it branches / falls to the 'false' block. Not profitable, may end up increasing code size.
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for needing the DAG node to print pre-legalize extended value types, and
to get better debug messages with target-specific nodes.
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with a general target hook to identify rematerializable instructions. Some
instructions are only rematerializable with specific operands, such as loads
from constant pools, while others are always rematerializable. This hook
allows both to be identified as being rematerializable with the same
mechanism.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37643 91177308-0d34-0410-b5e6-96231b3b80d8
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