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path: root/lib/CodeGen/TwoAddressInstructionPass.cpp
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2010-07-03Detect and handle COPY in many places.Jakob Stoklund Olesen
This code is transitional, it will soon be possible to eliminate isExtractSubreg, isInsertSubreg, and isMoveInstr in most places. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107547 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-02- Two-address pass should not assume unfolding is always successful.Evan Cheng
- X86 unfolding should check if the instructions being unfolded has memoperands. If there is no memoperands, then it must assume conservative alignment. If this would introduce an expensive sse unaligned load / store, then unfoldMemoryOperand etc. should not unfold the instruction. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107509 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-22When unfolding a load, avoid assuming which instruction thatDan Gohman
kill and dead flags will end up on. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106520 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-22Fix the new load-unfolding code to update LiveVariable's dead flags,Dan Gohman
in addition to the kill flags. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106512 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-21Teach two-address lowering how to unfold a load to open up commutingDan Gohman
opportunities. For example, this lets it emit this: movq (%rax), %rcx addq %rdx, %rcx instead of this: movq %rdx, %rcx addq (%rax), %rcx in the case where %rdx has subsequent uses. It's the same number of instructions, and usually the same encoding size on x86, but it appears faster, and in general, it may allow better scheduling for the load. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106493 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-18Only run CoalesceExtSubRegs when we can expect LiveIntervalAnalysis to clean upJakob Stoklund Olesen
the inserted INSERT_SUBREGs after us. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106345 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-15Add some missing checks for the case where the extract_subregs areBob Wilson
combined to an insert_subreg, i.e., where the destination register is larger than the source. We need to check that the subregs can be composed for that case in a symmetrical way to the case when the destination is smaller. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106004 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-15Generalize the pre-coalescing of extract_subregs feeding reg_sequences,Bob Wilson
replacing the overly conservative checks that I had introduced recently to deal with correctness issues. This makes a pretty noticable difference in our testcases where reg_sequences are used. I've updated one test to check that we no longer emit the unnecessary subreg moves. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105991 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-09Allow target to place 2-address pass inserted copies in better spots. Thumb2 ↵Evan Cheng
will use this to try to avoid breaking up IT blocks. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105745 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-07Fix a mistake in my previous change r105437: don't access operand 2 and assumeBob Wilson
that it is an immediate before checking that the instruction is an EXTRACT_SUBREG. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105585 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-03Add some missing checks in TwoAddressInstructionPass::CoalesceExtSubRegs.Bob Wilson
Check that all the instructions are in the same basic block, that the EXTRACT_SUBREGs write to the same subregs that are being extracted, and that the source and destination registers are in the same regclass. Some of these constraints can be relaxed with a bit more work. Jakob suggested that the loop that checks for subregs when NewSubIdx != 0 should use the "nodbg" iterator, so I made that change here, too. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105437 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-02Slightly change the meaning of the reMaterialize target hook when the originalJakob Stoklund Olesen
instruction defines subregisters. Any existing subreg indices on the original instruction are preserved or composed with the new subreg index. Also substitute multiple operands mentioning the original register by using the new MachineInstr::substituteRegister() function. This is necessary because there will soon be <imp-def> operands added to non read-modify-write partial definitions. This instruction: %reg1234:foo = FLAP %reg1234<imp-def> will reMaterialize(%reg3333, bar) like this: %reg3333:bar-foo = FLAP %reg333:bar<imp-def> Finally, replace the TargetRegisterInfo pointer argument with a reference to indicate that it cannot be NULL. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105358 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-02Rename canCombinedSubRegIndex method to something more grammatically correctBob Wilson
and tidy up the comment describing it. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105339 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-02Fix an obvious mistake: don't change the operands until all of them have beenBob Wilson
checked and it is safe to proceed with the changes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105304 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-29Handle composed subreg indices when processing REQ_SEQUENCE instructions.Jakob Stoklund Olesen
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105066 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-21- Change MachineInstr::findRegisterDefOperandIdx so it can also look for defsEvan Cheng
that are aliases of the specified register. - Rename modifiesRegister to definesRegister since it's looking a def of the specific register or one of its super-registers. It's not looking for def of a sub-register or alias that could change the specified register. - Added modifiesRegister to look for defs of aliases. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104377 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-19TwoAddressInstructionPass doesn't really know how to merge live intervals whenJakob Stoklund Olesen
lowering REG_SEQUENCE instructions. Insert copies for REG_SEQUENCE sources not killed to avoid breaking later passes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104146 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-17Fix PR7175. Insert copies of a REG_SEQUENCE source if it is used by other ↵Evan Cheng
REG_SEQUENCE instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103994 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-17Fix PR7156. If the sources of a REG_SEQUENCE are all IMPLICIT_DEF's. Replace ↵Evan Cheng
it with an IMPLICIT_DEF rather than deleting it or else it would be left without a def. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103984 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-17Careful with reg_sequence coalescing to not to overwrite sub-register indices.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103971 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-14Teach two-address pass to do some coalescing while eliminating REG_SEQUENCEEvan Cheng
instructions. e.g. %reg1026<def> = VLDMQ %reg1025<kill>, 260, pred:14, pred:%reg0 %reg1027<def> = EXTRACT_SUBREG %reg1026, 6 %reg1028<def> = EXTRACT_SUBREG %reg1026<kill>, 5 ... %reg1029<def> = REG_SEQUENCE %reg1028<kill>, 5, %reg1027<kill>, 6, %reg1028, 7, %reg1027, 8, %reg1028, 9, %reg1027, 10, %reg1030<kill>, 11, %reg1032<kill>, 12 After REG_SEQUENCE is eliminated, we are left with: %reg1026<def> = VLDMQ %reg1025<kill>, 260, pred:14, pred:%reg0 %reg1029:6<def> = EXTRACT_SUBREG %reg1026, 6 %reg1029:5<def> = EXTRACT_SUBREG %reg1026<kill>, 5 The regular coalescer will not be able to coalesce reg1026 and reg1029 because it doesn't know how to combine sub-register indices 5 and 6. Now 2-address pass will consult the target whether sub-registers 5 and 6 of reg1026 can be combined to into a larger sub-register (or combined to be reg1026 itself as is the case here). If it is possible, it will be able to replace references of reg1026 with reg1029 + the larger sub-register index. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103835 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-13If REG_SEQUENCE source is livein, copy it first. Also, update livevariables ↵Evan Cheng
information when a copy is introduced. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103680 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-12Code clean up.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103538 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-11Ensure REG_SEQUENCE source operands are unique.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103449 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-10Clear RegSequences vector after eliminating REG_SEQUENCE instructions.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103435 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-06Add a DebugLoc argument to TargetInstrInfo::copyRegToReg, so that itDan Gohman
doesn't have to guess. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103194 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-05Move REG_SEQUENCE removal to 2addr pass.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103109 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-23Ignore dbg_value's.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99321 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-03Add MachineRegisterInfo::hasOneUse and hasOneNonDBGUse.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97663 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-02Swap parameters of isSafeToMove and isSafeToReMat for consistency.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97578 91177308-0d34-0410-b5e6-96231b3b80d8
2010-02-11Don't allow DBG_VALUE to affect codegen.Dale Johannesen
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95889 91177308-0d34-0410-b5e6-96231b3b80d8
2010-02-10Skip debug info in a couple of places.Dale Johannesen
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95814 91177308-0d34-0410-b5e6-96231b3b80d8
2010-02-09move target-independent opcodes out of TargetInstrInfoChris Lattner
into TargetOpcodes.h. #include the new TargetOpcodes.h into MachineInstr. Add new inline accessors (like isPHI()) to MachineInstr, and start using them throughout the codebase. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95687 91177308-0d34-0410-b5e6-96231b3b80d8
2010-02-09Skip DEBUG_VALUE in some places where it was affecting codegen.Dale Johannesen
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95647 91177308-0d34-0410-b5e6-96231b3b80d8
2010-01-05Change errs() to dbgs().David Greene
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@92565 91177308-0d34-0410-b5e6-96231b3b80d8
2009-12-03improve portability to avoid conflicting with std::next in c++'0x.Chris Lattner
Patch by Howard Hinnant! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@90365 91177308-0d34-0410-b5e6-96231b3b80d8
2009-11-18Fix PR5300.Jakob Stoklund Olesen
When TwoAddressInstructionPass deletes a dead instruction, make sure that all register kills are accounted for. The 2-addr register does not get special treatment. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89246 91177308-0d34-0410-b5e6-96231b3b80d8
2009-11-14- Change TargetInstrInfo::reMaterialize to pass in TargetRegisterInfo.Evan Cheng
- If destination is a physical register and it has a subreg index, use the sub-register instead. This fixes PR5423. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@88745 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-25Remove includes of Support/Compiler.h that are no longer needed after theNick Lewycky
VISIBILITY_HIDDEN removal. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85043 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-25Remove VISIBILITY_HIDDEN from class/struct found inside anonymous namespaces.Nick Lewycky
Chris claims we should never have visibility_hidden inside any .cpp file but that's still not true even after this commit. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85042 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-09Factor out LiveIntervalAnalysis' code to determine whether an instructionDan Gohman
is trivially rematerializable and integrate it into TargetInstrInfo::isTriviallyReMaterializable. This way, all places that need to know whether an instruction is rematerializable will get the same answer. This enables the useful parts of the aggressive-remat option by default -- using AliasAnalysis to determine whether a memory location is invariant, and removes the questionable parts -- rematting operations with virtual register inputs that may not be live everywhere. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83687 91177308-0d34-0410-b5e6-96231b3b80d8
2009-09-03Overhaul the TwoAddressInstructionPass to simplify the logic, especiallyBob Wilson
for the complicated case where one register is tied to multiple destinations. This avoids the extra scan of instruction operands that was introduced by my recent change. I also pulled some code out into a separate TryInstructionTransform method, added more comments, and renamed some variables. Besides all those changes, this takes care of a FIXME in the code regarding an assumption about there being a single tied use of a register when converting to a 3-address form. I'm not aware of cases where that assumption is violated, but the code now only attempts to transform an instruction, either by commuting its operands or by converting to a 3-address form, for the simple case where there is a single pair of tied operands. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80945 91177308-0d34-0410-b5e6-96231b3b80d8
2009-09-02Rearrange code to eliminate redundancy and avoid gotos.Bob Wilson
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80798 91177308-0d34-0410-b5e6-96231b3b80d8
2009-09-01Avoid calling removeVirtualRegisterKilled which iterates over the operandsBob Wilson
to find the kill, since we already have the operand. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80736 91177308-0d34-0410-b5e6-96231b3b80d8
2009-09-01Refactor some code into separate functions. No functional changes.Bob Wilson
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80733 91177308-0d34-0410-b5e6-96231b3b80d8
2009-09-01Move use of LV inside condition that guards for null LV.Bob Wilson
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80731 91177308-0d34-0410-b5e6-96231b3b80d8
2009-09-01Fix pr4843: When an instruction has multiple destination registers that areBob Wilson
tied to different source registers, the TwoAddressInstructionPass needs to be smarter. Change it to check before replacing a source register whether that source register is tied to a different destination register, and if so, defer handling it until a subsequent iteration. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80654 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-31Use early exit and reduce indentation.Bob Wilson
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80631 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-31If the tied registers are already the same, there is no need to changeBob Wilson
them. Move the code to make that change inside the conditional. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80630 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-23remove some DOUTsChris Lattner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79812 91177308-0d34-0410-b5e6-96231b3b80d8
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