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path: root/lib/CodeGen/TwoAddressInstructionPass.cpp
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2012-07-25Disable rematerialization in TwoAddressInstructionPass.Manman Ren
It is redundant; RegisterCoalescer will do the remat if it can't eliminate the copy. Collected instruction counts before and after this. A few extra instructions are generated due to spilling but it is normal to see these kinds of changes with almost any small codegen change, according to Jakob. This also fixed rdar://11830760 where xor is expected instead of movi0. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160749 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-18Fix a somewhat nasty crasher in PR13378. This crashes inside ofChandler Carruth
LiveIntervals due to the two-addr pass generating bogus MI code. The crux of the issue was a loop nesting problem. The intent of the code which attempts to transform instructions before converting them to two-addr form is to defer and reprocess any transformed instructions as the second processing is likely to have more opportunities to coalesce copies, etc. Unfortunately, there was one section of processing that was not deferred -- the INSERT_SUBREG rewriting. Due to quirks of how this rewriting proceeded, not only did it occur early, it removed the bits of information needed for the deferred processing to correctly generate the necessary two address form (specifically inserting a copy), but didn't trigger any immediate assertions and produced what appeared to be already valid two-address from code. Thus, the assertion only fired much later in the pipeline. The fix is to hoist the transformation logic up layer to where it can more firmly defer all further processing, and to teach the normal processing to handle an edge case previously handled as part of the transformation logic. This edge case (already matched tied register operands) needs to *not* defer any steps. As has been brought up repeatedly in the process: wow does this code need refactoring. I *may* squeeze in some time to at least bring sanity to this loop... but wow... =] Thanks to Jakob for helpful hints on the way here, and the review. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160443 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-17Add some trace output to TwoAddressInstructionPass.Jakob Stoklund Olesen
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160380 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-15Reapply r160194, switching to use LV information for finding local kills.Chandler Carruth
The notable fix is to look at any dependencies attached to the kill instruction (or other instructions between MI nad the kill) where the dependencies are specific to the register in question. The old code implicitly handled this by rejecting the transform if *any* other uses were found within the block, but after the start point. The new code directly finds the kill, and has to re-use the existing dependency scan to check for non-kill uses. This was caught by self-host, but I found the bug via inspection and use of absurd assert scaffolding to compute the kills in two ways and compare them. So I have no useful testcase for this other than "bootstrap". I'd work harder to reduce a test case if this particular code were likely to live for a long time. Thanks to Benjamin Kramer for reviewing the fix itself. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160228 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-13Revert r160194, which switched to use LV information for finding localChandler Carruth
kills. This is causing miscompiles that I'm working on tracking down. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160196 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-13Use the LiveVariables information to efficiently get local kills. ThisChandler Carruth
removes the largest scaling problem in the test cases from PR13225 when ASan is switched to insert basic blocks in the natural CFG order. It may also solve some scaling problems for more normal code with large numbers of basic blocks and variables. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160194 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-02Added assertion in getVRegDef of MachineRegisterInfo to make sure the virtualManman Ren
register does not have multiple definitions. Modified TwoAddressInstructionPass to use getUniqueVRegDef instead of getVRegDef. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159545 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-25Handle <undef> operands in TwoAddressInstructionPass.Jakob Stoklund Olesen
When the source register to a 2-addr instruction is undefined, there is no need to attempt any transformations - simply replace the source register with the destination register. This also comes up when lowering IMPLICIT_DEF instructions - make sure the <undef> flag is moved to the new partial register def operand: %vreg8<def> = INSERT_SUBREG %vreg9<undef>, %vreg0<kill>, sub_16bit rewrite undef: %vreg8<def> = INSERT_SUBREG %vreg8<undef>, %vreg0<kill>, sub_16bit convert to: %vreg8:sub_16bit<def,read-undef> = COPY %vreg0<kill> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159120 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-05misched: API for minimum vs. expected latency.Andrew Trick
Minimum latency determines per-cycle scheduling groups. Expected latency determines critical path and cost. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158021 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-20Properly constrain register classes in 2-addr.Jakob Stoklund Olesen
X86 has 2-addr instructions with different constraints on the tied def and use operands. One is GR32, one is GR32_NOSP. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157149 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-18Teach two-address pass to update the "source" map so it doesn't perform aEvan Cheng
non-profitable commute using outdated info. The test case would still fail because of poor pre-RA schedule. That will be fixed by MI scheduler. rdar://11472010 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157038 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-07Add an MF argument to TRI::getPointerRegClass() and TII::getRegClass().Jakob Stoklund Olesen
The getPointerRegClass() hook can return register classes that depend on the calling convention of the current function (ptr_rc_tailcall). So far, we have been able to infer the calling convention from the subtarget alone, but as we add support for multiple calling conventions per target, that no longer works. Patch by Yiannis Tsiouris! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156328 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-03Fix two-address pass's aggressive instruction commuting heuristics. It's meantEvan Cheng
to catch cases like: %reg1024<def> = MOV r1 %reg1025<def> = MOV r0 %reg1026<def> = ADD %reg1024, %reg1025 r0 = MOV %reg1026 By commuting ADD, it let coalescer eliminate all of the copies. However, there was a bug in the heuristics where it ended up commuting the ADD in: %reg1024<def> = MOV r0 %reg1025<def> = MOV 0 %reg1026<def> = ADD %reg1024, %reg1025 r0 = MOV %reg1026 That did no benefit but rather ensure the last MOV would not be coalesced. rdar://11355268 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156048 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-03Added TargetRegisterInfo::getAllocatableClass.Andrew Trick
The ensures that virtual registers always belong to an allocatable class. If your target attempts to create a vreg for an operand that has no allocatable register subclass, you will crash quickly. This ensures that targets define register classes as intended. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156046 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-09Patch r153892 for PR11861 apparently broke an external project (see PR12493).Lang Hames
This patch restores TwoAddressInstructionPass's pre-r153892 behaviour when rescheduling instructions in TryInstructionTransform. Hopefully this will fix PR12493. To refix PR11861, lowering of INSERT_SUBREGS is deferred until after the copy that unties the operands is emitted (this seems to be a more appropriate fix for that issue anyway). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154338 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-04REG_SEQUENCE expansion to COPY instructions wasn't taking account of sub ↵Pete Cooper
register indices on the source registers. No simple test case git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154051 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-04Remove spurious debug output.Jakob Stoklund Olesen
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154032 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-02During two-address lowering, rescheduling an instruction does not untieLang Hames
operands. Make TryInstructionTransform return false to reflect this. Fixes PR11861. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153892 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-10RegAlloc superpass: includes phi elimination, coalescing, and scheduling.Andrew Trick
Creates a configurable regalloc pipeline. Ensure specific llc options do what they say and nothing more: -reglloc=... has no effect other than selecting the allocator pass itself. This patch introduces a new umbrella flag, "-optimize-regalloc", to enable/disable the optimizing regalloc "superpass". This allows for example testing coalscing and scheduling under -O0 or vice-versa. When a CodeGen pass requires the MachineFunction to have a particular property, we need to explicitly define that property so it can be directly queried rather than naming a specific Pass. For example, to check for SSA, use MRI->isSSA, not addRequired<PHIElimination>. CodeGen transformation passes are never "required" as an analysis ProcessImplicitDefs does not require LiveVariables. We have a plan to massively simplify some of the early passes within the regalloc superpass. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150226 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-03whitespaceAndrew Trick
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149671 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-24Set correct <def,undef> flags when lowering REG_SEQUENCE.Jakob Stoklund Olesen
A REG_SEQUENCE instruction is lowered into a sequence of partial defs: %vreg7:ssub_0<def,undef> = COPY %vreg20:ssub_0 %vreg7:ssub_1<def> = COPY %vreg2 %vreg7:ssub_2<def> = COPY %vreg2 %vreg7:ssub_3<def> = COPY %vreg2 The first def needs an <undef> flag to indicate it is the beginning of the live range, while the other defs are read-modify-write. Previously, we depended on LiveIntervalAnalysis to notice and fix the missing <def,undef>, but that solution was never robust, it was causing problems with ProcessImplicitDefs and the lowering of chained REG_SEQUENCE instructions. This fixes PR11841. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148879 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-24Preserve <def,undef> flags in CoalesceExtSubRegs.Jakob Stoklund Olesen
This won't have an effect until EliminateRegSequences() starts setting the undef flags. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148779 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-18Fix ISD::REG_SEQUENCE to accept physical registers and change ↵Pete Cooper
TwoAddressInstructionPass to insert copies for any physical reg operands of the REG_SEQUENCE git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148377 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-07Add bundle aware API for querying instruction properties and switch the codeEvan Cheng
generator to it. For non-bundle instructions, these behave exactly the same as the MC layer API. For properties like mayLoad / mayStore, look into the bundle and if any of the bundled instructions has the property it would return true. For properties like isPredicable, only return true if *all* of the bundled instructions have the property. For properties like canFoldAsLoad, isCompare, conservatively return false for bundles. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146026 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-03Simplify code. No functionality change.Benjamin Kramer
-3% on ARMDissasembler.cpp. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145773 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-16Disable expensive two-address optimizations at -O0. rdar://10453055Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144806 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-16Disable the assertion again. Looks like fastisel is still generating bad ↵Evan Cheng
kill markers. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144804 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-16Revert r144568 now that r144730 has fixed the fast-isel kill marker bug.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144776 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-16If the 2addr instruction has other kills, don't move it below any other uses ↵Evan Cheng
since we don't want to extend other live ranges. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144772 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-16RescheduleKillAboveMI() must backtrack to before the rescheduled DBG_VALUE ↵Evan Cheng
instructions. rdar://10451185 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144771 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-16Process all uses first before defs to accurately capture register liveness. ↵Evan Cheng
rdar://10449480 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144770 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-15Set SeenStore to true to prevent loads from being moved; also eliminates a ↵Evan Cheng
non-deterministic behavior. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144628 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-14Avoid dereferencing off the beginning of lists.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144569 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-14At -O0, multiple uses of a virtual registers in the same BB are being markedEvan Cheng
"kill". This looks like a bug upstream. Since that's going to take some time to understand, loosen the assertion and disable the optimization when multiple kills are seen. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144568 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-14Teach two-address pass to re-schedule two-address instructions (or the killEvan Cheng
instructions of the two-address operands) in order to avoid inserting copies. This fixes the few regressions introduced when the two-address hack was disabled (without regressing the improvements). rdar://10422688 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144559 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-23PR10998: It is not legal to sink an instruction past the terminator of a ↵Eli Friedman
block; make sure we don't do that. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140428 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-29Add an isSSA() flag to MachineRegisterInfo.Jakob Stoklund Olesen
This flag is true from isel to register allocation when the machine function is required to be in SSA form. The TwoAddressInstructionPass and PHIElimination passes clear the flag. The SSA flag wil be used by the machine code verifier to check for SSA form, and eventually an assertion can enforce it in +Asserts builds. This will catch the common target error of creating machine code with multiple defs of a virtual register. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136532 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-28- Rename TargetInstrDesc, TargetOperandInfo to MCInstrDesc and MCOperandInfo andEvan Cheng
sink them into MC layer. - Added MCInstrInfo, which captures the tablegen generated static data. Chang TargetInstrInfo so it's based off MCInstrInfo. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134021 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-27More refactoring. Move getRegClass from TargetOperandInfo to TargetInstrInfo.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133944 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-18Simplify code. No change in functionality.Benjamin Kramer
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133350 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-07Fix an issue where the two-address conversion pass incorrectly rewrites untiedCameron Zwarich
operands to an early clobber register. This fixes <rdar://problem/9566076>. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132738 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-02Catch more cases where 2-address pass should 3-addressify instructions. ↵Evan Cheng
rdar://9002648. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126811 91177308-0d34-0410-b5e6-96231b3b80d8
2011-02-10After 3-addressifying a two-address instruction, update the register maps; ↵Evan Cheng
add a missing check when considering whether it's profitable to commute. rdar://8977508. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@125259 91177308-0d34-0410-b5e6-96231b3b80d8
2011-01-10Simplify a bunch of isVirtualRegister() and isPhysicalRegister() logic.Jakob Stoklund Olesen
These functions not longer assert when passed 0, but simply return false instead. No functional change intended. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123155 91177308-0d34-0410-b5e6-96231b3b80d8
2011-01-09Shrink a BitVector that didn't mean to store bits for all physical registers.Jakob Stoklund Olesen
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123108 91177308-0d34-0410-b5e6-96231b3b80d8
2011-01-07Do not model all INLINEASM instructions as having unmodelled side effects.Evan Cheng
Instead encode llvm IR level property "HasSideEffects" in an operand (shared with IsAlignStack). Added MachineInstrs::hasUnmodeledSideEffects() to check the operand when the instruction is an INLINEASM. This allows memory instructions to be moved around INLINEASM instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123044 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-19StrongPHIElimination will never run before TwoAddressInstructionPass.Cameron Zwarich
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122197 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-19Remove some checks for StrongPHIElim. These checks make it impossible to use anCameron Zwarich
alternative register allocator that does not require LiveIntervals by specifying it on the command-line for a target that has StrongPHIElimination enabled by default. These checks are pretty meaningless anyways, since StrongPHIElimination and PHIElimination are never used at the same time. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122176 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-17Fix crash compiling a QQQQ REG_SEQUENCE for a Neon vld3_lane operation.Bob Wilson
Radar 8776599 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122018 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-14Fix a minor bug in two-address pass. It was missing a commute opportunity.Evan Cheng
regB = move RCX regA = op regB, regC RAX = move regA where both regB and regC are killed. If regB is constrainted to non-compatible physical registers but regC is not constrainted at all, then it's better to commute the instruction. movl %edi, %eax shlq $32, %rcx leaq (%rcx,%rax), %rax => movl %edi, %eax shlq $32, %rcx orq %rcx, %rax rdar://8762995 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121793 91177308-0d34-0410-b5e6-96231b3b80d8
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