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path: root/lib/CodeGen/SimpleRegisterCoalescing.cpp
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2009-09-21Merge in fix for PR4910.Tanya Lattner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_26@82428 91177308-0d34-0410-b5e6-96231b3b80d8
2009-09-08Merge 81204 from mainline (with minor tweak).Tanya Lattner
When remat'ing and destination virtual register has a sub-register index. Make sure the sub-register class matches the register class of the remat'ed instruction definition register class. git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_26@81270 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-10Modified VNInfo. The "copy" member is now a union which holds the copy for a ↵Lang Hames
register interval, or the defining register for a stack interval. Access is via getCopy/setCopy and getReg/setReg. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78620 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-07Another coalescer bug. When a dead copy is eliminated, transfer the kill to ↵Evan Cheng
a def of the exact register rather than a super-register. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78376 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-05Rename a variable to make MSVC happy.Benjamin Kramer
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78202 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-05Another nasty coalescer bug (is there another kind):Evan Cheng
After coalescing reg1027's def and kill are both at the same point: %reg1027,0.000000e+00 = [56,814:0) 0@70-(814) bb5: 60 %reg1027<def> = t2MOVr %reg1027, 14, %reg0, %reg0 68 %reg1027<def> = t2LDRi12 %reg1027<kill>, 8, 14, %reg0 76 t2CMPzri %reg1038<kill,undef>, 0, 14, %reg0, %CPSR<imp-def> 84 %reg1027<def> = t2MOVr %reg1027, 14, %reg0, %reg0 96 t2Bcc mbb<bb5,0x2030910>, 1, %CPSR<kill> Do not remove the kill marker on t2LDRi12. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78178 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-03Fix a coaelescer bug. If a copy val# is extended to eliminate a ↵Evan Cheng
non-trivially coalesced copy, and the copy kills its source register. Trim the source register's live range to the last use if possible. This fixes up kill marker to make the scavenger happy. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77967 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-31Use setPreservesAll and setPreservesCFG in CodeGen passes.Dan Gohman
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77754 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-29inline the global 'getInstrOperandRegClass' function into its callersChris Lattner
now that TargetOperandInfo does the heavy lifting. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77508 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-27Avoid build warnings.Mike Stump
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77271 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-25More migration to raw_ostream, the water has dried up around the iostream hole.Daniel Dunbar
- Some clients which used DOUT have moved to DEBUG. We are deprecating the "magic" DOUT behavior which avoided calling printing functions when the statement was disabled. In addition to being unnecessary magic, it had the downside of leaving code in -Asserts builds, and of hiding potentially unnecessary computations. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77019 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-22Make some changes suggested by Bill and Evan.David Greene
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76775 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-21Add some support for iterative coalescers to calculate a joined liveDavid Greene
range's weight properly. This is turned off right now in the sense that you'll get an assert if you get into a situation that can only be caused by an iterative coalescer. All other code paths operate exactly as before so there is no functional change with this patch. The asserts should be disabled if/when an iterative coalescer gets added to trunk. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76680 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-21Cross RC coalescing is now on by default.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76519 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-20Fix some sub-reg coalescing bugs where the coalescer wasn't updating the ↵Evan Cheng
resulting interval's register class. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76458 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-18Catch more coalescing opportunities.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76282 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-18Enable cross register class coalescing.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76281 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-17Simplify some more.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76239 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-17Simplify the coalescer (finally!) by making ↵Evan Cheng
LiveIntervals::processImplicitDefs a little more aggressive and teaching liveintervals to make use of isUndef marker on MachineOperands. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76223 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-16Let callers decide the sub-register index on the def operand of ↵Evan Cheng
rematerialized instructions. Avoid remat'ing instructions whose def have sub-register indices for now. It's just really really hard to get all the cases right. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75900 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-15ShortenDeadCopySrcLiveRange needs to be more conservative in multi-kill ↵Evan Cheng
situations. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75838 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-14llvm_unreachable->llvm_unreachable(0), LLVM_UNREACHABLE->llvm_unreachable.Torok Edwin
This adds location info for all llvm_unreachable calls (which is a macro now) in !NDEBUG builds. In NDEBUG builds location info and the message is off (it only prints "UREACHABLE executed"). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75640 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-14Fix pr4544. When remating, make sure the destination register fits the ↵Evan Cheng
instruction definition. It may be mismatched due to sub-register coalescing. No test case yet because the code doesn't trigger until 75408 is re-applied. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75572 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-11assert(0) -> LLVM_UNREACHABLE.Torok Edwin
Make llvm_unreachable take an optional string, thus moving the cerr<< out of line. LLVM_UNREACHABLE is now a simple wrapper that makes the message go away for NDEBUG builds. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75379 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-10Remove TargetInstrInfo::CommuteChangesDestination and added ↵Evan Cheng
findCommutedOpIndices which returns the operand indices which are swapped (when applicable). This allows for some code clean up and future enhancements. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75264 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-09Improved tracking of value number kills. VN kills are now representedLang Hames
as an (index,bool) pair. The bool flag records whether the kill is a PHI kill or not. This code will be used to enable splitting of live intervals containing PHI-kills. A slight change to live interval weights introduced an extra spill into lsr-code-insertion (outside the critical sections). The test condition has been updated to reflect this. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75097 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-01Remove special handling of implicit_def. Fix a couple more bugs in ↵Evan Cheng
liveintervalanalysis and coalescer handling of implicit_def. Note, isUndef marker must be placed even on implicit_def def operand or else the scavenger will not ignore it. This is necessary because -O0 path does not use liveintervalanalysis, it treats implicit_def just like any other def. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74601 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-22Fix another register coalescer crash: forgot to check if the instruction ↵Evan Cheng
being updated has already been coalesced. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73898 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-18- Update register allocation hint after coalescing. This is done by the ↵Evan Cheng
target since the hint is target dependent. This is important for ARM register pair hints. - Register allocator should resolve the second part of the hint (register number) before passing it to the target since it knows virtual register to physical register mapping. - More fixes to get ARM load / store double word working. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73671 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-17VNInfo cleanup.Lang Hames
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73634 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-16Rename RemoveCopiesFromValNo to TurnCopiesFromValNoToImpDefs.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73479 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-16If a val# is defined by an implicit_def and it is being removed, all of the ↵Evan Cheng
copies off the val# were removed. This causes problem later since the scavenger will see uses of registers without defs. The proper solution is to change the copies into implicit_def's instead. TurnCopyIntoImpDef turns a copy into implicit_def and remove the val# defined by it. This causes an scavenger assertion later if the def reaches other blocks. Disable the transformation if the value live interval extends beyond its def block. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73478 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-15Part 1.Evan Cheng
- Change register allocation hint to a pair of unsigned integers. The hint type is zero (which means prefer the register specified as second part of the pair) or entirely target dependent. - Allow targets to specify alternative register allocation orders based on allocation hint. Part 2. - Use the register allocation hint system to implement more aggressive load / store multiple formation. - Aggressively form LDRD / STRD. These are formed *before* register allocation. It has to be done this way to shorten live interval of base and offset registers. e.g. v1025 = LDR v1024, 0 v1026 = LDR v1024, 0 => v1025,v1026 = LDRD v1024, 0 If this transformation isn't done before allocation, v1024 will overlap v1025 which means it more difficult to allocate a register pair. - Even with the register allocation hint, it may not be possible to get the desired allocation. In that case, the post-allocation load / store multiple pass must fix the ldrd / strd instructions. They can either become ldm / stm instructions or back to a pair of ldr / str instructions. This is work in progress, not yet enabled. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73381 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-14Move register allocation preference (or hint) from LiveInterval to ↵Evan Cheng
MachineRegisterInfo. This allows more passes to set them. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73346 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-02Update to in-place spilling framework. Includes live interval scaling and ↵Lang Hames
trivial rewriter. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72729 91177308-0d34-0410-b5e6-96231b3b80d8
2009-05-11Fixed PR4090.Lang Hames
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@71495 91177308-0d34-0410-b5e6-96231b3b80d8
2009-04-30Join cross class copies using getCommonSubClass()Jakob Stoklund Olesen
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@70513 91177308-0d34-0410-b5e6-96231b3b80d8
2009-04-30Add a smarter heuristic to determine when to coalesce a virtual register ↵Evan Cheng
with a physical one. More specifically, it avoid tying a virtual register in the loop with a physical register defined / used outside the loop. When it determines it's not profitable, it will use the physical register as the allocation preference instead. This is *not* turned on by default. Testing indicates this is just as likely to pessimize code. The main issue seems to be allocation preference doesn't work effectively. That will change once I've taught register allocator "swapping". git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@70503 91177308-0d34-0410-b5e6-96231b3b80d8
2009-04-28Move getMatchingSuperReg() out of coalescer and into TargetRegisterInfo.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@70309 91177308-0d34-0410-b5e6-96231b3b80d8
2009-04-28Don't coalesce a physical register with an incompatible virtual register.Jakob Stoklund Olesen
If the physical register does not belong to the virtual register's regclass, don't coalesce. The physical register could be an invalid operand for an instruction using the vreg. The regclass matching is done after determining the actual subregisters being copied. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@70298 91177308-0d34-0410-b5e6-96231b3b80d8
2009-04-27Don't skip the CopyMI when removing kill markers.Owen Anderson
This should have no effect on generated code, but makes the intermediate state of the coalescer more sane. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@70238 91177308-0d34-0410-b5e6-96231b3b80d8
2009-04-23Update comments.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@69919 91177308-0d34-0410-b5e6-96231b3b80d8
2009-04-23Fix an obvious type.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@69918 91177308-0d34-0410-b5e6-96231b3b80d8
2009-04-08Implement support for using modeling implicit-zero-extension on x86-64Dan Gohman
with SUBREG_TO_REG, teach SimpleRegisterCoalescing to coalesce SUBREG_TO_REG instructions (which are similar to INSERT_SUBREG instructions), and teach the DAGCombiner to take advantage of this on targets which support it. This eliminates many redundant zero-extension operations on x86-64. This adds a new TargetLowering hook, isZExtFree. It's similar to isTruncateFree, except it only applies to actual definitions, and not no-op truncates which may not zero the high bits. Also, this adds a new optimization to SimplifyDemandedBits: transform operations like x+y into (zext (add (trunc x), (trunc y))) on targets where all the casts are no-ops. In contexts where the high part of the add is explicitly masked off, this allows the mask operation to be eliminated. Fix the DAGCombiner to avoid undoing these transformations to eliminate casts on targets where the casts are no-ops. Also, this adds a new two-address lowering heuristic. Since two-address lowering runs before coalescing, it helps to be able to look through copies when deciding whether commuting and/or three-address conversion are profitable. Also, fix a bug in LiveInterval::MergeInClobberRanges. It didn't handle the case that a clobber range extended both before and beyond an existing live range. In that case, multiple live ranges need to be added. This was exposed by the new subreg coalescing code. Remove 2008-05-06-SpillerBug.ll. It was bugpoint-reduced, and the spiller behavior it was looking for no longer occurrs with the new instruction selection. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68576 91177308-0d34-0410-b5e6-96231b3b80d8
2009-03-30Fix grammar-o in comment.Bill Wendling
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68057 91177308-0d34-0410-b5e6-96231b3b80d8
2009-03-11My last coalescer fix introduced a subtler one. It's aborting a commuting ↵Evan Cheng
optimization too late and left the live intervals to be out of sync with instructions. This fixes 8b10b. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@66715 91177308-0d34-0410-b5e6-96231b3b80d8
2009-03-11Two coalescer fixes in one.Evan Cheng
1. Use the same value# to represent unknown values being merged into sub-registers. 2. When coalescer commute an instruction and the destination is a physical register, update its sub-registers by merging in the extended ranges. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@66610 91177308-0d34-0410-b5e6-96231b3b80d8
2009-02-22If a use operand is marked isKill, don't forget to add kill to its live ↵Evan Cheng
interval as well. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@65279 91177308-0d34-0410-b5e6-96231b3b80d8
2009-02-09Fix another case ShortenDeadCopySrcLiveRange is shortening too much. No test ↵Evan Cheng
case possible since I don't know what to grep for. :-( git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@64125 91177308-0d34-0410-b5e6-96231b3b80d8
2009-02-08Fix PR3486. Fix a bug in code that manually patch physical register live ↵Evan Cheng
interval after its sub-register is coalesced with a virtual register. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@64082 91177308-0d34-0410-b5e6-96231b3b80d8
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