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2011-10-18Fix a bug in the legalization of vector anyext-load and trunc-store. Mem ↵Nadav Rotem
Index starts with zero. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142434 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-18Fix a DAG combiner assertion failure when constant folding BUILD_VECTORS.Bob Wilson
svn r139159 caused SelectionDAG::getConstant() to promote BUILD_VECTOR operands with illegal types, even before type legalization. For this testcase, that led to one BUILD_VECTOR with i16 operands and another with promoted i32 operands, which triggered the assertion. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142370 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-18Fix a bunch of unused variable warnings when doing a releaseDuncan Sands
build with gcc-4.6. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142350 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-18Fix comment to refer to correct instructionHal Finkel
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142334 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-17Correct over-zealous removal of hack.Bill Wendling
Some code want to check that *any* call within a function has the 'returns twice' attribute, not just that the current function has one. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142221 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-17Now that we have the ReturnsTwice function attribute, this method isBill Wendling
obsolete. Check the attribute instead. <rdar://problem/8031714> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142212 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-17Removed set, but unused variable.Chad Rosier
Patch by Joe Abbey <jabbey@arxan.com>. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142206 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-16Enable element promotion type legalization by deafault.Nadav Rotem
Changed tests which assumed that vectors are legalized by widening them. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142152 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-16Let printf do the formatting instead aligning strings ourselves.Benjamin Kramer
While at it, merge some format strings. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142140 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-15Move the legalization of vector loads and stores into LegalizeVectorOps. In someNadav Rotem
cases we need the second type-legalization pass in order to support all cases. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142060 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-15Clear out the landing pad to call site map for each function.Bill Wendling
This isn't put into the 'clear()' method because the information needs to stick around (at least for a little bit) after the selection DAG is built. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142032 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-14Fix typo. "__sync_fetch_and-xor_4" should be "__sync_fetch_and_xor_4".Jim Grosbach
Pointed out by George Russell. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141956 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-12Encode register class constreaints in inline asm instructions.Jakob Stoklund Olesen
The inline asm operand constraint is initially encoded in the virtual register for the operand, but that register class may change during coalescing, and the original constraint is lost. Encode the original register class as part of the flag word for each inline asm operand. This makes it possible to recover the actual constraint required by inline asm, just like we can for normal instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141833 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-12Use a utility from MathExtras to clarify a check and avoid undefined ↵Eli Friedman
behavior. Based on patch by Ahmed Charles. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141829 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-12Fix a thinko that Nick noticed. The previous code actually worked asDan Gohman
intended, but only by accident. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141779 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-12Use an existing function.Jakob Stoklund Olesen
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141763 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-11Formatting.Eric Christopher
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141728 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-11Add support for legalization of vector SHL/SRA/SRL instructionsNadav Rotem
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141667 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-11Add support for legalization of vector trunc-store where the saved scalar ↵Nadav Rotem
type is illegal (for example, v2i16 on systems where the smallest store size is i32) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141661 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-11Cleanup the trunc-store legalization code and add asserts.Nadav Rotem
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141659 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-07Thread the chain through the eh.sjlj.setjmp intrinsic, like it's documented toBill Wendling
do. This will be useful later on with the new SJLJ stuff. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141416 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-06Remove the old atomic instrinsics. autoupgrade functionality is included ↵Eli Friedman
with this patch. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141333 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-05Modify the mapping from landing pad to call sites to accept more than one callBill Wendling
site. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141226 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-05Small refactoring. Cache the FunctionInfo->MBB into a local variable.Bill Wendling
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141221 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-05Simplify EXTRACT_SUBREG emission.Jakob Stoklund Olesen
EXTRACT_SUBREG is emitted as %dst = COPY %src:sub, so there is no need to constrain the %dst register class. RegisterCoalescer will apply the necessary constraints if it decides to eliminate the COPY. The %src register class does need to be constrained to something with the right sub-registers, though. This is currently done manually with COPY_TO_REGCLASS nodes. They can possibly be removed after this patch. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141207 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-05Simplify INSERT_SUBREG emission.Jakob Stoklund Olesen
The register class created by INSERT_SUBREG and SUBREG_TO_REG must be legal and support the SubIdx sub-registers. The new getSubClassWithSubReg() hook can compute that. This may create INSERT_SUBREG instructions defining a larger register class than the sub-register being inserted. That is OK, RegisterCoalescer will constrain the register class as needed when it eliminates the INSERT_SUBREG instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141198 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-04Create a mapping between the landing pad basic block and the call site index ↵Bill Wendling
for later use. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141125 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-01Moved type construction out of the loop and added an assert on the legality ↵Nadav Rotem
of the type. Formatted lines to the 80 char limit. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140952 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-30When inferring the pointer alignment, if the global doesn't have an initializerBill Wendling
and the alignment is 0 (i.e., it's defined globally in one file and declared in another file) it could get an alignment which is larger than the ABI allows for that type, resulting in aligned moves being used for unaligned loads. For instance, in file A.c: struct S s; In file B.c: struct { // something long }; extern S s; void foo() { struct S p = s; // ... } this copy is a 'memcpy' which is turned into a series of 'movaps' instructions on X86. But this is wrong, because 'struct S' has alignment of 4, not 16. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140902 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-30Promote comment to doxycomment. Adjust whitespace. No functionality change.Nick Lewycky
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140899 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-30Move getCommonSubClass() into TRI.Jakob Stoklund Olesen
It will soon need the context. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140896 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-29Clean up uses of switch instructions so they are not dependent on the ↵Eli Friedman
operand ordering. Patch by Stepan Dyatkovskiy. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140803 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-29Use the local we already set up.Eric Christopher
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140745 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-28Strip off pointer casts when looking at the eh.sjlj.functioncontext's argument.Bill Wendling
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140678 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-28Create and use an llvm.eh.sjlj.functioncontext intrinsic.Bill Wendling
This intrinsic is used to pass the index of the function context to the back-end for further processing. The back-end is in charge of filling in the rest of the entries. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140676 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-27Rename AddSelectionDAGCSEId() to addSelectionDAGCSEId().Jim Grosbach
Naming conventions consistency. No functional change. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140636 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-27Cleanup PromoteIntOp_EXTRACT_VECTOR_ELT and PromoteIntRes_SETCC.Nadav Rotem
Add a new method: getAnyExtOrTrunc and use it to replace the manual check. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140603 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-27Revert r140463; The patch assumes that <4 x i1> is saved to memory as 4 x i8,Nadav Rotem
while the decision is to bit-pack small values. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140601 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-25[vector-select] Address one of the issues in pr10902. EXTRACT_VECTOR_ELEMENTNadav Rotem
SDNodes may return values which are wider than the incoming element types. In this patch we fix the integer promotion of these nodes. Fixes spill-q.ll when running -promote-elements. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140471 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-24Implement Duncan's suggestion to use the result of getSetCCResultType if it ↵Nadav Rotem
is legal (this is always the case for scalars), otherwise use the promoted result type. Fix test/CodeGen/X86/vsplit-and.ll when promote-elements is enabled. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140464 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-24[Vector-Select] Address one of the problems in 10902.Nadav Rotem
When generating the trunc-store of i1's, we need to use the vector type and not the scalar type. This patch fixes the assertion in CodeGen/Generic/bool-vector.ll when running with -promote-elements. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140463 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-23Tweak the handling of MERGE_VALUES nodes: remove the need forDuncan Sands
DecomposeMERGE_VALUES to "know" that results are legalized in a particular order, by passing it the number of the result being legalized (the type legalization core provides this, it just needs to be passed on). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140373 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-23Vector-Select: Address one of the problems in pr10902. Add handling for theNadav Rotem
integer-promotion of CONCAT_VECTORS. Test: test/CodeGen/X86/widen_shuffle-1.ll This patch fixes the above tests (when running in with -promote-elements). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140372 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-22Fix SimplifySelectCC to add newly created nodes to the DAGCombinerDan Gohman
worklist, as it may be possible to perform further optimization on them. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140349 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-22Constrain register classes instead of emitting copies.Jakob Stoklund Olesen
Sometimes register class constraints are trivial, like GR32->GR32_NOSP, or GPR->rGPR. Teach InstrEmitter to simply constrain the virtual register instead of emitting a copy in these cases. Normally, these copies are handled by the coalescer. This saves some coalescer work. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140340 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-21[VECTOR-SELECT] Address one of the bugs in pr10902.Nadav Rotem
Vector SetCC result types need to be type-legalized. This code worked before because scalar result types are known to be legal. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140249 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-21Lower ARM adds/subs to add/sub after adding optional CPSR operand.Andrew Trick
This is still a hack until we can teach tblgen to generate the optional CPSR operand rather than an implicit CPSR def. But the strangeness is now limited to the selection DAG. ADD/SUB MI's no longer have implicit CPSR defs, nor do we allow flag setting variants of these opcodes in machine code. There are several corner cases to consider, and getting one wrong would previously lead to nasty miscompilation. It's not the first time I've debugged one, so this time I added enough verification to ensure it won't happen again. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140228 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-20Add a DAGCombine for subvector extracts to remove useless chains ofBruno Cardoso Lopes
subvector inserts and extracts. Initial patch by Rackover, Zvi with some tweak done by me. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140204 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-20Restore hasPostISelHook tblgen flag.Andrew Trick
No functionality change. The hook makes it explicit which patterns require "special" handling. i.e. it self-documents tblgen deficiencies. I plan to add verification in ExpandISelPseudos and Thumb2SizeReduce to catch any missing hasPostISelHooks. Otherwise it's too fragile. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140160 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-20ARM isel bug fix for adds/subs operands.Andrew Trick
Modified ARMISelLowering::AdjustInstrPostInstrSelection to handle the full gamut of CPSR defs/uses including instructins whose "optional" cc_out operand is not really optional. This allowed removal of the hasPostISelHook to simplify the .td files and make the implementation more robust. Fixes rdar://10137436: sqlite3 miscompile git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140134 91177308-0d34-0410-b5e6-96231b3b80d8
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