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2012-02-10Put instruction names into an indexed string table on the side, removing a ↵Benjamin Kramer
pointer from MCInstrDesc. Make them accessible through MCInstrInfo. They are only used for debugging purposes so this doesn't have an impact on performance. X86MCTargetDesc.o goes from 630K to 461K on x86_64. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150245 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-06[unwind removal] Remove all of the code for the dead 'unwind' instruction. ThereBill Wendling
were no 'unwind' instructions being generated before this, so this is in effect a no-op. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149906 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-05Add additional documentation to the extract-and-trunc dagcombine optimization.Nadav Rotem
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149823 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-05Convert assert(0) to llvm_unreachableCraig Topper
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149816 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-05reapply the patches reverted in r149470 that reenable ConstantDataArray,Chris Lattner
but with a critical fix to the SelectionDAG code that optimizes copies from strings into immediate stores: the previous code was stopping reading string data at the first nul. Address this by adding a new argument to llvm::getConstantStringInfo, preserving the behavior before the patch. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149800 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-04[fast-isel] HandlePHINodesInSuccessorBlocks() can promite i8 and i16 types too.Chad Rosier
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149730 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-03Handle all live physreg defs in the same place.Jakob Stoklund Olesen
SelectionDAG has 4 different ways of passing physreg defs to users. Collect all of the uses at the same time, and pass all of them to MI->setPhysRegsDeadExcept() to mark the remaining defs dead. The setPhysRegsDeadExcept() function will soon add the required implicit-defs to instructions with register mask operands. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149708 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-03The type-legalizer often scalarizes code. One of the common patterns is ↵Nadav Rotem
extract-and-truncate. In this patch we optimize this pattern and convert the sequence into extract op of a narrow type. This allows the BUILD_VECTOR dag optimizations to construct efficient shuffle operations in many cases. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149692 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-01fix cmakeAndrew Trick
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149553 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-01VLIW specific scheduler framework that utilizes deterministic finite ↵Andrew Trick
automaton (DFA). This new scheduler plugs into the existing selection DAG scheduling framework. It is a top-down critical path scheduler that tracks register pressure and uses a DFA for pipeline modeling. Patch by Sergei Larin! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149547 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-01SwitchInst refactoring.Stepan Dyatkovskiy
The purpose of refactoring is to hide operand roles from SwitchInst user (programmer). If you want to play with operands directly, probably you will need lower level methods than SwitchInst ones (TerminatorInst or may be User). After this patch we can reorganize SwitchInst operands and successors as we want. What was done: 1. Changed semantics of index inside the getCaseValue method: getCaseValue(0) means "get first case", not a condition. Use getCondition() if you want to resolve the condition. I propose don't mix SwitchInst case indexing with low level indexing (TI successors indexing, User's operands indexing), since it may be dangerous. 2. By the same reason findCaseValue(ConstantInt*) returns actual number of case value. 0 means first case, not default. If there is no case with given value, ErrorIndex will returned. 3. Added getCaseSuccessor method. I propose to avoid usage of TerminatorInst::getSuccessor if you want to resolve case successor BB. Use getCaseSuccessor instead, since internal SwitchInst organization of operands/successors is hidden and may be changed in any moment. 4. Added resolveSuccessorIndex and resolveCaseIndex. The main purpose of these methods is to see how case successors are really mapped in TerminatorInst. 4.1 "resolveSuccessorIndex" was created if you need to level down from SwitchInst to TerminatorInst. It returns TerminatorInst's successor index for given case successor. 4.2 "resolveCaseIndex" converts low level successors index to case index that curresponds to the given successor. Note: There are also related compatability fix patches for dragonegg, klee, llvm-gcc-4.0, llvm-gcc-4.2, safecode, clang. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149481 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-01Revert Chris' commits up to r149348 that started causing VMCoreTests unit ↵Argyrios Kyrtzidis
test to fail. These are: r149348 r149351 r149352 r149354 r149356 r149357 r149361 r149362 r149364 r149365 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149470 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-31remove the last vestiges of llvm::GetConstantStringInfo, in CodeGen.Chris Lattner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149356 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-31rework this logic to not depend on the last argument to GetConstantStringInfo,Chris Lattner
which is going away. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149348 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-31Remove the now-dead llvm.eh.exception and llvm.eh.selector intrinsics.Bill Wendling
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149331 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-31Remove the eh.exception and eh.selector intrinsics. Also remove a hack to copyBill Wendling
over the catch information. The catch information is now tacked to the invoke instruction. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149326 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-31Use the correct ShiftAmtTy for creating shifts after legalization. PR11881. ↵Eli Friedman
Not committing a testcase because I think it will be too fragile. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149315 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-27continue making the world safe for ConstantDataVector. At this point,Chris Lattner
we should (theoretically optimize and codegen ConstantDataVector as well as ConstantVector. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149116 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-26eliminate the Constant::getVectorElements method. There are better (andChris Lattner
more robust) ways to do what it was doing now. Also, add static methods for decoding a ShuffleVector mask. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149028 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-25use ConstantVector::getSplat in a few places.Chris Lattner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148929 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-25Use the right method to get the # elements in a CDS.Chris Lattner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148897 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-24add more support for ConstantDataSequentialChris Lattner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148802 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-20More dead code removal (using -Wunreachable-code)David Blaikie
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148578 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-18Add a RegisterMaskSDNode class.Jakob Stoklund Olesen
This SelectionDAG node will be attached to call nodes by LowerCall(), and eventually becomes a MO_RegisterMask MachineOperand on the MachineInstr representing the call instruction. LowerCall() will attach a register mask that depends on the calling convention. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148436 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-18Fix a bug in the type-legalization of vector integers. When we bitcast one ↵Nadav Rotem
vector type to another, we must not bitcast the result if one type is widened while the other is promoted. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148383 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-18Fix ISD::REG_SEQUENCE to accept physical registers and change ↵Pete Cooper
TwoAddressInstructionPass to insert copies for any physical reg operands of the REG_SEQUENCE git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148377 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-17Transform: (EXTRACT_VECTOR_ELT( VECTOR_SHUFFLE )) -> EXTRACT_VECTOR_ELT.Nadav Rotem
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148337 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-17Teach DAG combiner to turn a BUILD_VECTOR of UNDEFs into an UNDEF of vector ↵Craig Topper
type. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148297 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-17Changed flag operand of ISD::FP_ROUND to TargetConstant as it should not get ↵Pete Cooper
checked for legalisation git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148275 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-16Refactor variables unused under non-assert builds (& remove two entirely ↵David Blaikie
unused variables). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148230 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-16Changed intrinsic ID operand to a target constant as its not used in any ↵Pete Cooper
arithmetic so should not be checked in legalisation git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148228 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-15[AVX] Optimize x86 VSELECT instructions using SimplifyDemandedBits.Nadav Rotem
We know that the blend instructions only use the MSB, so if the mask is sign-extended then we can convert it into a SHL instruction. This is a common pattern because the type-legalizer sign-extends the i1 type which is used by the LLVM-IR for the condition. Added a new optimization in SimplifyDemandedBits for SIGN_EXTEND_INREG -> SHL. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148225 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-15Return an ArrayRef from ShuffleVectorSDNode::getMask and push it through ↵Benjamin Kramer
CodeGen. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148218 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-15DAGCombiner: Deduplicate code.Benjamin Kramer
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148217 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-15Truncate of undef is just undef of smaller size.Craig Topper
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148205 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-13DAGCombine's logic for forming pre- and post- indexed loads / stores were beingEvan Cheng
overly conservative. It was concerned about cases where it would prohibit folding simple [r, c] addressing modes. e.g. ldr r0, [r2] ldr r1, [r2, #4] => ldr r0, [r2], #4 ldr r1, [r2] Change the logic to look for such cases which allows it to form indexed memory ops more aggressively. rdar://10674430 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148086 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-12Added FPOW, FEXP, FLOG to PromoteNode so that custom actions can be set to ↵Pete Cooper
Promote for those operations. Sorry, no test case yet git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148050 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-12Allow targets to select source order pre-RA scheduler.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148033 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-11On AVX, we can load v8i32 at a time. The bug happens when two uneven loads ↵Nadav Rotem
are used. When we load the v12i32 type, the GenWidenVectorLoads method generates two loads: v8i32 and v4i32 and attempts to use CONCAT_VECTORS to join them. In this fix I concat undef values to widen the smaller value. The test "widen_load-2.ll" also exposes this bug on AVX. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147964 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-11Teach the X86 instruction selection to do some heroic transforms toChandler Carruth
detect a pattern which can be implemented with a small 'shl' embedded in the addressing mode scale. This happens in real code as follows: unsigned x = my_accelerator_table[input >> 11]; Here we have some lookup table that we look into using the high bits of 'input'. Each entity in the table is 4-bytes, which means this implicitly gets turned into (once lowered out of a GEP): *(unsigned*)((char*)my_accelerator_table + ((input >> 11) << 2)); The shift right followed by a shift left is canonicalized to a smaller shift right and masking off the low bits. That hides the shift right which x86 has an addressing mode designed to support. We now detect masks of this form, and produce the longer shift right followed by the proper addressing mode. In addition to saving a (rather large) instruction, this also reduces stalls in Intel chips on benchmarks I've measured. In order for all of this to work, one part of the DAG needs to be canonicalized *still further* than it currently is. This involves removing pointless 'trunc' nodes between a zextload and a zext. Without that, we end up generating spurious masks and hiding the pattern. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147936 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-10Add 'llvm_unreachable' to passify GCC's understanding of the constraintsChandler Carruth
of several newly un-defaulted switches. This also helps optimizers (including LLVM's) recognize that every case is covered, and we should assume as much. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147861 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-10Remove unnecessary default cases in switches that cover all enum values.David Blaikie
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147855 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-10Fix a bug in the legalization of shuffle vectors. When we emulate shuffles ↵Nadav Rotem
using BUILD_VECTORS we may be using a BV of different type. Make sure to cast it back. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147851 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-07Replace some uses of hasNUsesOfValue(0, X) with !hasAnyUseOfValue(X)Craig Topper
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147733 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-07Add some DAG combines for SUBC/SUBE. If nothing uses the carry/borrow out of ↵Craig Topper
subc, turn it into a sub. Turn (subc x, x) into 0 with no borrow. Turn (subc x, 0) into x with no borrow. Turn (subc -1, x) into (xor x, -1) with no borrow. Turn sube with no borrow in into subc. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147728 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-06Add comment.Chad Rosier
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147696 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-05Prevent a DAGCombine from firing where there are two uses ofChandler Carruth
a combined-away node and the result of the combine isn't substantially smaller than the input, it's just canonicalized. This is the first part of a significant (7%) performance gain for Snappy's hot decompression loop. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147604 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-04Allow vector shuffle normalizing to use concat vector even if the sources ↵Craig Topper
are commuted in the shuffle mask. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147527 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-04Implement VECTOR_SHUFFLE canonicalizations during DAG combine.Craig Topper
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147525 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-03Turn a few more inline asm errors into "emitErrors" instead of fatal errors.Chris Lattner
Before we'd get: $ clang t.c fatal error: error in backend: Invalid operand for inline asm constraint 'i'! Now we get: $ clang t.c t.c:16:5: error: invalid operand for inline asm constraint 'i'! "movq (%4), %%mm0\n" ^ Which at least gets us the inline asm that is the problem. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147502 91177308-0d34-0410-b5e6-96231b3b80d8
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