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U utils/TableGen/FastISelEmitter.cpp
--- Reverse-merging r107943 into '.':
U test/CodeGen/X86/fast-isel.ll
U test/CodeGen/X86/fast-isel-loads.ll
U include/llvm/Target/TargetLowering.h
U include/llvm/Support/PassNameParser.h
U include/llvm/CodeGen/FunctionLoweringInfo.h
U include/llvm/CodeGen/CallingConvLower.h
U include/llvm/CodeGen/FastISel.h
U include/llvm/CodeGen/SelectionDAGISel.h
U lib/CodeGen/LLVMTargetMachine.cpp
U lib/CodeGen/CallingConvLower.cpp
U lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
U lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp
U lib/CodeGen/SelectionDAG/FastISel.cpp
U lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
U lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp
U lib/CodeGen/SelectionDAG/InstrEmitter.cpp
U lib/CodeGen/SelectionDAG/TargetLowering.cpp
U lib/Target/XCore/XCoreISelLowering.cpp
U lib/Target/XCore/XCoreISelLowering.h
U lib/Target/X86/X86ISelLowering.cpp
U lib/Target/X86/X86FastISel.cpp
U lib/Target/X86/X86ISelLowering.h
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107987 91177308-0d34-0410-b5e6-96231b3b80d8
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a DBG_VALUE after a terminator, or emitting any instructions before an EH_LABEL.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107943 91177308-0d34-0410-b5e6-96231b3b80d8
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disabled and then never turned back on again. Adjust some tests, one because
this change avoids an unnecessary instruction, and the other to make it
continue testing what it was intended to test.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107941 91177308-0d34-0410-b5e6-96231b3b80d8
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if the inline ASM doesn't need a stack frame.
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EXTRACT_SUBREG no longer appears as a machine instruction. Use COPY instead.
Add isCopy() checks in many places using isMoveInstr() and isExtractSubreg().
The isMoveInstr hook will be removed later.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107879 91177308-0d34-0410-b5e6-96231b3b80d8
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few more idioms.
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Debug info intrinsics win for now.
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prefer to materialize as local constants. This fixes the clang
bootstrap abort.
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for consistency sake.
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didn't create a new block, don't reset the insert position.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107813 91177308-0d34-0410-b5e6-96231b3b80d8
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a separate DCE pass over MachineInstrs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107804 91177308-0d34-0410-b5e6-96231b3b80d8
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a bunch of stuff, to allow the target-independent calling convention
logic to be employed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107800 91177308-0d34-0410-b5e6-96231b3b80d8
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position when emitting multiple blocks when executing a custom
inserter.
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around everywhere, and also give it an InsertPt member, to enable isel
to operate at an arbitrary position within a block, rather than just
appending to a block.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107791 91177308-0d34-0410-b5e6-96231b3b80d8
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instance, rather than pointers to all of FunctionLoweringInfo's
members.
This eliminates an NDEBUG ABI sensitivity.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107789 91177308-0d34-0410-b5e6-96231b3b80d8
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allow target-specific fast-isel code to make use of it directly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107787 91177308-0d34-0410-b5e6-96231b3b80d8
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code can do calling-convention queries. This obviates OutputArgReg.
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than assuming a target will custom lower them. Targets which do so should
exlicitly mark them as having custom lowerings. PR7454.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107734 91177308-0d34-0410-b5e6-96231b3b80d8
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SelectBasicBlock doesn't needs its BasicBlock argument.
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the block before calling the expansion hook. And don't
put EFLAGS in a mbb's live-in list twice.
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which do not depend on SelectionDAG.
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ensures remat'ed loads from fixed slots have the right alignments.
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PrologEpilog code, and use it to determine whether
the asm forces stack alignment or not. gcc consistently
does not do this for GCC-style asms; Apple gcc inconsistently
sometimes does it for asm blocks. There is no
convenient place to put a bit in either the SDNode or
the MachineInstr form, so I've added an extra operand
to each; unlovely, but it does allow for expansion for
more bits, should we need it. PR 5125. Some
existing testcases are affected.
The operand lists of the SDNode and MachineInstr forms
are indexed with awesome mnemonics, like "2"; I may
fix this someday, but not now. I'm not making it any
worse. If anyone is inspired I think you can find all
the right places from this patch.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107393 91177308-0d34-0410-b5e6-96231b3b80d8
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doing the work manually.
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from a Value to a Type, because it doesn't actually care about
the Value.
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available in a register. This is pretty primitive, but it reduces the
number of instructions in common testcases by 4%.
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SelectionDAGBuilder::getValue into a helper function, with fixes to
use DenseMaps safely.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107371 91177308-0d34-0410-b5e6-96231b3b80d8
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value if the search fails.
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this could break something (but doesn't seem to).
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of getPhysicalRegisterRegClass with it.
If we want to make a copy (or estimate its cost), it is better to use the
smallest class as more efficient operations might be possible.
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can't be changed arbitrarily by the DAGCombiner without checking if it is
running after legalization.
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have to be registers, per gcc documentation. This affects
the logic for determining what "g" should lower to. PR 7393.
A couple of existing testcases are affected.
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This produces terrible but correct code.
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