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2011-01-25Provide an interface to transfer SDDbgValue from one SDNode to another.Devang Patel
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124245 91177308-0d34-0410-b5e6-96231b3b80d8
2011-01-25Resolve DanglingDbgValue of PHI nodes where the use follows dbg.value ↵Devang Patel
intrinisic. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124203 91177308-0d34-0410-b5e6-96231b3b80d8
2011-01-25This assertion is too restrictive, it does not apply for dangling dbg value ↵Devang Patel
nodes (nodes where dbg.value intrinsic preceds use of the value). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124202 91177308-0d34-0410-b5e6-96231b3b80d8
2011-01-24Speculatively revert r124138.Devang Patel
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124142 91177308-0d34-0410-b5e6-96231b3b80d8
2011-01-24Resolve DanglingDbgValue of PHI nodes where the use follows dbg.value ↵Devang Patel
intrinisic. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124138 91177308-0d34-0410-b5e6-96231b3b80d8
2011-01-24Temporarily workaround JM/lencod miscompile (SIGSEGV).Andrew Trick
rdar://problem/8893967 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124137 91177308-0d34-0410-b5e6-96231b3b80d8
2011-01-23Null initialize a few variables flagged byTed Kremenek
clang's -Wuninitialized-experimental warning. While these don't look like real bugs, clang's -Wuninitialized-experimental analysis is stricter than GCC's, and these fixes have the benefit of being general nice cleanups. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124073 91177308-0d34-0410-b5e6-96231b3b80d8
2011-01-21Enable support for precise scheduling of the instruction selectionAndrew Trick
DAG. Disable using "-disable-sched-cycles". For ARM, this enables a framework for modeling the cpu pipeline and counting stalls. It also activates several heuristics to drive scheduling based on the model. Scheduling is inherently imprecise at this stage, and until spilling is improved it may defeat attempts to schedule. However, this framework provides greater control over tuning codegen. Although the flag is not target-specific, it should have very little affect on the default scheduler used by x86. The only two changes that affect x86 are: - scheduling a high-latency operation bumps the current cycle so independent operations can have their latency covered. i.e. two independent 4 cycle operations can produce results in 4 cycles, not 8 cycles. - Two operations with equal register pressure impact and no latency-based stalls on their uses will be prioritized by depth before height (height is irrelevant if no stalls occur in the schedule below this point). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123971 91177308-0d34-0410-b5e6-96231b3b80d8
2011-01-21Convert -enable-sched-cycles and -enable-sched-hazard to -disableAndrew Trick
flags. They are still not enable in this revision. Added TargetInstrInfo::isZeroCost() to fix a fundamental problem with the scheduler's model of operand latency in the selection DAG. Generalized unit tests to work with sched-cycles. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123969 91177308-0d34-0410-b5e6-96231b3b80d8
2011-01-20My editor's indent went crazy. Fix.Eric Christopher
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123909 91177308-0d34-0410-b5e6-96231b3b80d8
2011-01-20Expand invalid return values for umulo and smulo. Handle these similarlyEric Christopher
to add/sub by doing the normal operation and then checking for overflow afterwards. This generally relies on the DAG handling the later invalid operations as well. Fixes the 64-bit part of rdar://8622122 and rdar://8774702. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123908 91177308-0d34-0410-b5e6-96231b3b80d8
2011-01-20Selection DAG scheduler register pressure heuristic fixes.Andrew Trick
Added a check for already live regs before claiming HighRegPressure. Fixed a few cases of checking the wrong number of successors. Added some tracing until these heuristics are better understood. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123892 91177308-0d34-0410-b5e6-96231b3b80d8
2011-01-20Use only one API at a time.Eric Christopher
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123866 91177308-0d34-0410-b5e6-96231b3b80d8
2011-01-20If we can, lower the multiply part of a umulo/smulo call to a libcallEric Christopher
with an invalid type then split the result and perform the overflow check normally. Fixes the 32-bit parts of rdar://8622122 and rdar://8774702. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123864 91177308-0d34-0410-b5e6-96231b3b80d8
2011-01-18Remove unused variables found by gcc-4.6's -Wunused-but-set-variable.Jeffrey Yasskin
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123707 91177308-0d34-0410-b5e6-96231b3b80d8
2011-01-18Remove checking that prevented overlapping CALLSEQ_START/CALLSEQ_ENDStuart Hastings
ranges, add legalizer support for nested calls. Necessary for ARM byval support. Radar 7662569. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123704 91177308-0d34-0410-b5e6-96231b3b80d8
2011-01-17Fix an off-by-one error in ctpop combining.Benjamin Kramer
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123664 91177308-0d34-0410-b5e6-96231b3b80d8
2011-01-17Add a DAGCombine to turn (ctpop x) u< 2 into (x & x-1) == 0.Benjamin Kramer
This shaves off 4 popcounts from the hacked 186.crafty source. This is enabled even when a native popcount instruction is available. The combined code is one operation longer but it should be faster nevertheless. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123621 91177308-0d34-0410-b5e6-96231b3b80d8
2011-01-16reapply my fix for PR8961 with a tweak to properly handleChris Lattner
multi-instruction sequences like calls. Many thanks to Jakob for finding a testcase. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123559 91177308-0d34-0410-b5e6-96231b3b80d8
2011-01-15Add an assert so we don't silently miscompile ctpop for bit widths > 128.Benjamin Kramer
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123549 91177308-0d34-0410-b5e6-96231b3b80d8
2011-01-15Reimplement CTPOP legalization with the "best" algorithm fromBenjamin Kramer
http://graphics.stanford.edu/~seander/bithacks.html#CountBitsSetParallel In a silly microbenchmark on a 65 nm core2 this is 1.5x faster than the old code in 32 bit mode and about 2x faster in 64 bit mode. It's also a lot shorter, especially when counting 64 bit population on a 32 bit target. I hope this is fast enough to replace Kernighan-style counting loops even when the input is rather sparse. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123547 91177308-0d34-0410-b5e6-96231b3b80d8
2011-01-14Delete an assignment to ThisBB which isn't needed, and tidy up someDan Gohman
comments. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123479 91177308-0d34-0410-b5e6-96231b3b80d8
2011-01-14Support for precise scheduling of the instruction selection DAG,Andrew Trick
disabled in this checkin. Sorry for the large diffs due to refactoring. New functionality is all guarded by EnableSchedCycles. Scheduling the isel DAG is inherently imprecise, but we give it a best effort: - Added MayReduceRegPressure to allow stalled nodes in the queue only if there is a regpressure need. - Added BUHasStall to allow checking for either dependence stalls due to latency or resource stalls due to pipeline hazards. - Added BUCompareLatency to encapsulate and standardize the heuristics for minimizing stall cycles (vs. reducing register pressure). - Modified the bottom-up heuristic (now in BUCompareLatency) to prioritize nodes by their depth rather than height. As long as it doesn't stall, height is irrelevant. Depth represents the critical path to the DAG root. - Added hybrid_ls_rr_sort::isReady to filter stalled nodes before adding them to the available queue. Related Cleanup: most of the register reduction routines do not need to be templates. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123468 91177308-0d34-0410-b5e6-96231b3b80d8
2011-01-14Set the insertion point correctly for instructions generated by load folding:Chris Lattner
they should go *before* the new instruction not after it. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123420 91177308-0d34-0410-b5e6-96231b3b80d8
2011-01-13Fix r123346 to handle scalar types too.Dan Gohman
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123352 91177308-0d34-0410-b5e6-96231b3b80d8
2011-01-12Apply the patch from PR8958, which allows llc to get slightlyDan Gohman
further on the associated testcase before aborting. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123346 91177308-0d34-0410-b5e6-96231b3b80d8
2011-01-11Move ExpandAtomic into the integer expansion routines - it's only used there.Eric Christopher
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123202 91177308-0d34-0410-b5e6-96231b3b80d8
2011-01-10Fix PR 8916 (qv for analysis), at least the immediate problem.Dale Johannesen
There's an inherent tension in DAGCombine between assuming that things will be put in canonical form, and the Depth mechanism that disables transformations when recursion gets too deep. It would not surprise me if there's a lot of little bugs like this one waiting to be discovered. The mechanism seems fragile and I'd suggest looking at it from a design viewpoint. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123191 91177308-0d34-0410-b5e6-96231b3b80d8
2011-01-10Rename TargetFrameInfo into TargetFrameLowering. Also, put couple of FIXMEs ↵Anton Korobeynikov
and fixes here and there. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123170 91177308-0d34-0410-b5e6-96231b3b80d8
2011-01-10Simplify a bunch of isVirtualRegister() and isPhysicalRegister() logic.Jakob Stoklund Olesen
These functions not longer assert when passed 0, but simply return false instead. No functional change intended. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123155 91177308-0d34-0410-b5e6-96231b3b80d8
2011-01-09Replace TargetRegisterInfo::printReg with a PrintReg class that also works ↵Jakob Stoklund Olesen
without a TRI instance. Print virtual registers numbered from 0 instead of the arbitrary FirstVirtualRegister. The first virtual register is printed as %vreg0. TRI::NoRegister is printed as %noreg. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123107 91177308-0d34-0410-b5e6-96231b3b80d8
2011-01-08Use an IndexedMap for LiveOutRegInfo to hide its dependence on ↵Jakob Stoklund Olesen
TargetRegisterInfo::FirstVirtualRegister. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123096 91177308-0d34-0410-b5e6-96231b3b80d8
2011-01-07Do not model all INLINEASM instructions as having unmodelled side effects.Evan Cheng
Instead encode llvm IR level property "HasSideEffects" in an operand (shared with IsAlignStack). Added MachineInstrs::hasUnmodeledSideEffects() to check the operand when the instruction is an INLINEASM. This allows memory instructions to be moved around INLINEASM instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123044 91177308-0d34-0410-b5e6-96231b3b80d8
2011-01-07Add ARM patterns to match EXTRACT_SUBVECTOR nodes.Bob Wilson
Also fix an off-by-one in SelectionDAGBuilder that was preventing shuffle vectors from being translated to EXTRACT_SUBVECTOR. Patch by Tim Northover. The test changes are needed to keep those spill-q tests from testing aligned spills and restores. If the only aligned stack objects are spill slots, we no longer realign the stack frame. Prior to this patch, an EXTRACT_SUBVECTOR was legalized by loading from the stack, which created an aligned frame index. Now, however, there is nothing except the spill slot in the stack frame, so I added an aligned alloca. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122995 91177308-0d34-0410-b5e6-96231b3b80d8
2011-01-07Change EXTRACT_SUBVECTOR to require a constant index.Bob Wilson
We were never generating any of these nodes with variable indices, and there was one legalizer function asserting on a non-constant index. If we ever have a need to support variable indices, we can add this back again. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122993 91177308-0d34-0410-b5e6-96231b3b80d8
2011-01-06Fix the other problem reported in PR8582. Testcase and patch byDuncan Sands
Nadav Rotem. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122983 91177308-0d34-0410-b5e6-96231b3b80d8
2011-01-06Add some fairly duplicated code to let type legalization split illegalEric Christopher
typed atomics. This will lower exclusively to libcalls at the moment. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122979 91177308-0d34-0410-b5e6-96231b3b80d8
2011-01-06Re-implement r122936 with proper target hooks. Now getMaxStoresPerMemcpyEvan Cheng
etc. takes an option OptSize. If OptSize is true, it would return the inline limit for functions with attribute OptSize. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122952 91177308-0d34-0410-b5e6-96231b3b80d8
2011-01-06Revert r122936. I'll re-implement the change.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122949 91177308-0d34-0410-b5e6-96231b3b80d8
2011-01-06r105228 reduced the memcpy / memset inline limit to 4 with -Os to avoid blowingEvan Cheng
up freebsd bootloader. However, this doesn't make much sense for Darwin, whose -Os is meant to optimize for size only if it doesn't hurt performance. rdar://8821501 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122936 91177308-0d34-0410-b5e6-96231b3b80d8
2011-01-06Avoid zero extend bit test operands to pointer type if all the masks fit inEvan Cheng
the original type of the switch statement key. rdar://8781238 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122935 91177308-0d34-0410-b5e6-96231b3b80d8
2011-01-05Optimize:Evan Cheng
r1025 = s/zext r1024, 4 r1026 = extract_subreg r1025, 4 to: r1026 = copy r1024 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122925 91177308-0d34-0410-b5e6-96231b3b80d8
2011-01-0580-cols.Eric Christopher
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122909 91177308-0d34-0410-b5e6-96231b3b80d8
2011-01-04Remove TODO, these appear to be implemented.Eric Christopher
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122849 91177308-0d34-0410-b5e6-96231b3b80d8
2011-01-02Try to reuse the value when lowering memset.Benjamin Kramer
This allows us to compile: void test(char *s, int a) { __builtin_memset(s, a, 15); } into 1 mul + 3 stores instead of 3 muls + 3 stores. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122710 91177308-0d34-0410-b5e6-96231b3b80d8
2011-01-02Lower the i8 extension in memset to a multiply instead of a potentially long ↵Benjamin Kramer
series of shifts and ors. We could implement a DAGCombine to turn x * 0x0101 back into logic operations on targets that doesn't support the multiply or it is slow (p4) if someone cares enough. Example code: void test(char *s, int a) { __builtin_memset(s, a, 4); } before: _test: ## @test movzbl 8(%esp), %eax movl %eax, %ecx shll $8, %ecx orl %eax, %ecx movl %ecx, %eax shll $16, %eax orl %ecx, %eax movl 4(%esp), %ecx movl %eax, 4(%ecx) movl %eax, (%ecx) ret after: _test: ## @test movzbl 8(%esp), %eax imull $16843009, %eax, %eax ## imm = 0x1010101 movl 4(%esp), %ecx movl %eax, 4(%ecx) movl %eax, (%ecx) ret git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122707 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-24Minor cleanup related to my latest scheduler changes.Andrew Trick
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122545 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-24Fix a few cases where the scheduler is not checking for phys reg copies. The ↵Andrew Trick
scheduling node may have a NULL DAG node, yuck. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122544 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-24Various bits of framework needed for precise machine-level selectionAndrew Trick
DAG scheduling during isel. Most new functionality is currently guarded by -enable-sched-cycles and -enable-sched-hazard. Added InstrItineraryData::IssueWidth field, currently derived from ARM itineraries, but could be initialized differently on other targets. Added ScheduleHazardRecognizer::MaxLookAhead to indicate whether it is active, and if so how many cycles of state it holds. Added SchedulingPriorityQueue::HasReadyFilter to allowing gating entry into the scheduler's available queue. ScoreboardHazardRecognizer now accesses the ScheduleDAG in order to get information about it's SUnits, provides RecedeCycle for bottom-up scheduling, correctly computes scoreboard depth, tracks IssueCount, and considers potential stall cycles when checking for hazards. ScheduleDAGRRList now models machine cycles and hazards (under flags). It tracks MinAvailableCycle, drives the hazard recognizer and priority queue's ready filter, manages a new PendingQueue, properly accounts for stall cycles, etc. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122541 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-24whitespaceAndrew Trick
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122539 91177308-0d34-0410-b5e6-96231b3b80d8
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