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2010-07-2380-col.Eric Christopher
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109205 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-22keep in 80 colsGabor Greif
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109122 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-22mass elimination of reliance on automatic iterator dereferencingGabor Greif
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109103 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-22Re-apply r109079 with fix.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109083 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-22Revert r109079, which broke a lot of CodeGen tests.Owen Anderson
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109082 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-22Initialize RegLimit only when register pressure is being tracked.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109079 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-21More register pressure aware scheduling work.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109064 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-21Teach bottom up pre-ra scheduler to track register pressure. Work in progress.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108991 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-19After a custom inserter, in a block which has constant instructions,Dan Gohman
update the current basic block in addition to the current insert position, so that they remain consistent. This fixes rdar://8204072. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108765 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-19ARM has to provide its own TargetLowering::findRepresentativeClass because ↵Evan Cheng
its scalar floating point registers alias its vector registers. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108761 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-19Teach computeRegisterProperties() to compute "representative" register class ↵Evan Cheng
for legal value types. A "representative" register class is the largest legal super-reg register class for a value type. e.g. On i386, GR32 is the rep register class for i8 / i16 / i32; on x86_64 it would be GR64. This property will be used by the register pressure tracking instruction scheduler. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108735 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-19Remove r108639 now that it is handled by InstCombine instead.Owen Anderson
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108688 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-18Add a DAGCombine xform to fold away redundant float->double->float ↵Owen Anderson
conversions around sqrt instructions. I am assured by people more knowledgeable than me that there are no rounding issues in eliminating this. This fixed <rdar://problem/8197504>. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108639 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-17Propagate alloca alignment information via variable size object frameEric Christopher
information. No functional change yet. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108583 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-16Revert r108369, sorting llvm.dbg.declare information by source position,Dan Gohman
since it doesn't work for front-ends which don't emit column information (which includes llvm-gcc in its present configuration), and doesn't work for clang for K&R style variables where the variables are declared in a different order from the parameter list. Instead, make a separate pass through the instructions to collect the llvm.dbg.declare instructions in order. This ensures that the debug information for variables is emitted in this order. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108538 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-16Use the source-order scheduler instead of the "fast" scheduler at -O0,Dan Gohman
because it's more likely to keep debug line information in its original order. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108496 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-16The SelectionDAGBuilder's handling of debug info, on rareDale Johannesen
occasions, caused code to be generated in a different order. All cases I've seen involved float softening in the type legalizer, and this could be perhaps be fixed there, but it's better not to generate things differently in the first place. 7797940 (6/29/2010..7/15/2010). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108484 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-15Revert. This isn't the correct way to go.Bill Wendling
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108478 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-15Handle code gen for the unreachable instruction if it's the only instruction inBill Wendling
the function. We'll just turn it into a "trap" instruction instead. The problem with not handling this is that it might generate a prologue without the equivalent epilogue to go with it: $ cat t.ll define void @foo() { entry: unreachable } $ llc -o - t.ll -relocation-model=pic -disable-fp-elim -unwind-tables .section __TEXT,__text,regular,pure_instructions .globl _foo .align 4, 0x90 _foo: ## @foo Leh_func_begin0: ## BB#0: ## %entry pushq %rbp Ltmp0: movq %rsp, %rbp Ltmp1: Leh_func_end0: ... The unwind tables then have bad data in them causing all sorts of problems. Fixes <rdar://problem/8096481>. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108473 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-15Split -enable-finite-only-fp-math to two options:Evan Cheng
-enable-no-nans-fp-math and -enable-no-infs-fp-math. All of the current codegen fp math optimizations only care whether the fp arithmetics arguments and results can never be NaN. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108465 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-15Fix crash reported in PR7653.Devang Patel
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108441 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-1480-col.Eric Christopher
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108381 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-14Properly restore DebugLoc after leaving the local constant area.Dan Gohman
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108364 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-14Delete fast-isel's trivial load optimization; it breaks debugging becauseDan Gohman
it can look past points where a debugger might modify user variables. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108336 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-14Don't propagate debug locations to instructions for materializingDan Gohman
constants, since they may not be emited near the other instructions which get the same line, and this confuses debug info. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108302 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-13In inline asm treat indirect 'X' constraint as 'm'.Dale Johannesen
This may not be right in all cases, but it's better than asserting which it was doing before. PR 7528. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108268 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-12Fix a typo and fit in 80 columns. Found by Bob Wilson.Rafael Espindola
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108164 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-12Convert some tab stops into spaces.Duncan Sands
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108130 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-11Use COPY for fast-isel bitconvert, but don't create cross-class copies.Jakob Stoklund Olesen
This doesn't change the behavior of SelectBitcast for X86. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108073 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-11Fix va_arg for doubles. With this patch VAARG nodes always contain theRafael Espindola
correct alignment information, which simplifies ExpandRes_VAARG a bit. The patch introduces a new alignment information to TargetLoweringInfo. This is needed since the two natural candidates cannot be used: * The 's' in target data: If this is set to the minimal alignment of any argument, getCallFrameTypeAlignment would return 4 for doubles on ARM for example. * The getTransientStackAlignment method. It is possible for an architecture to have argument less aligned than what we maintain the stack pointer. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108072 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-11Use COPY for extracting ImplicitDef'ed values from fast-isel instructions.Jakob Stoklund Olesen
This assumes that the registers can be copied which is probably a safe assumption. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108070 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-11Use COPY in FastISel everywhere it is safe and trivial.Jakob Stoklund Olesen
The remaining copyRegToReg calls actually check the return value (shock!), so we cannot trivially replace them with COPY instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108069 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-10Fix a bug in the code which re-inserts DBG_VALUE nodes after scheduling;Dan Gohman
if a block is split (by a custom inserter), the insert point may be in a different block than it was originally. This fixes 32-bit llvm-gcc bootstrap builds, and I haven't been able to reproduce it otherwise. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108060 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-10Emit COPY instructions instead of using copyRegToReg in InstrEmitter,Jakob Stoklund Olesen
ScheduleDAGEmit, TwoAddressLowering, and PHIElimination. This switches the bulk of register copies to using COPY, but many less used copyRegToReg calls remain. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108050 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-10Insert IMPLICIT_DEF instructions at the current insert position, notDan Gohman
at the end of the block. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108045 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-10Reapply bottom-up fast-isel, with several fixes for x86-32:Dan Gohman
- Check getBytesToPopOnReturn(). - Eschew ST0 and ST1 for return values. - Fix the PIC base register initialization so that it doesn't ever fail to end up the top of the entry block. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108039 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-09Clarify what mysterious check means.Bill Wendling
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108005 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-09--- Reverse-merging r107947 into '.':Bob Wilson
U utils/TableGen/FastISelEmitter.cpp --- Reverse-merging r107943 into '.': U test/CodeGen/X86/fast-isel.ll U test/CodeGen/X86/fast-isel-loads.ll U include/llvm/Target/TargetLowering.h U include/llvm/Support/PassNameParser.h U include/llvm/CodeGen/FunctionLoweringInfo.h U include/llvm/CodeGen/CallingConvLower.h U include/llvm/CodeGen/FastISel.h U include/llvm/CodeGen/SelectionDAGISel.h U lib/CodeGen/LLVMTargetMachine.cpp U lib/CodeGen/CallingConvLower.cpp U lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp U lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp U lib/CodeGen/SelectionDAG/FastISel.cpp U lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp U lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp U lib/CodeGen/SelectionDAG/InstrEmitter.cpp U lib/CodeGen/SelectionDAG/TargetLowering.cpp U lib/Target/XCore/XCoreISelLowering.cpp U lib/Target/XCore/XCoreISelLowering.h U lib/Target/X86/X86ISelLowering.cpp U lib/Target/X86/X86FastISel.cpp U lib/Target/X86/X86ISelLowering.h git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107987 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-09cache result of operator*Gabor Greif
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107980 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-09Re-apply bottom-up fast-isel, with fixes. Be very careful to avoid emittingDan Gohman
a DBG_VALUE after a terminator, or emitting any instructions before an EH_LABEL. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107943 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-09Reenable DAG combining for vector shuffles. It looks like it was temporarilyBob Wilson
disabled and then never turned back on again. Adjust some tests, one because this change avoids an unnecessary instruction, and the other to make it continue testing what it was intended to test. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107941 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-08Extension of r107506. Make sure that we don't mark a function as having a callBill Wendling
if the inline ASM doesn't need a stack frame. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107922 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-08Convert EXTRACT_SUBREG to COPY when emitting machine instrs.Jakob Stoklund Olesen
EXTRACT_SUBREG no longer appears as a machine instruction. Use COPY instead. Add isCopy() checks in many places using isMoveInstr() and isExtractSubreg(). The isMoveInstr hook will be removed later. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107879 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-08Merge the duplicated iabs optimization in DAGCombiner and let it detected a ↵Benjamin Kramer
few more idioms. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107868 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-08Revert 107840 107839 107813 107804 107800 107797 107791.Dan Gohman
Debug info intrinsics win for now. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107850 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-07Don't forward-declare registers for static allocas, which we'llDan Gohman
prefer to materialize as local constants. This fixes the clang bootstrap abort. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107840 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-07Fix -fast-isel-abort to check the right instruction.Dan Gohman
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107839 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-07Move getExtLoad() and (some) getLoad() DebugLoc argument after EVT argument ↵Evan Cheng
for consistency sake. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107820 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-07Not all custom inserters create new basic blocks. If the inserterDan Gohman
didn't create a new block, don't reset the insert position. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107813 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-07Implement bottom-up fast-isel. This has the advantage of not requiringDan Gohman
a separate DCE pass over MachineInstrs. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107804 91177308-0d34-0410-b5e6-96231b3b80d8
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