llvm - http://llvm.org

Age	Commit message (Expand)	Author
2011-06-27	During bottom up fast-isel, instructions emitted to materalize registers are ...	Devang Patel
2011-06-27	More refactoring. Move getRegClass from TargetOperandInfo to TargetInstrInfo.	Evan Cheng
2011-06-27	The index stored in the RegDefIter is one after the current index. When gett...	Owen Anderson
2011-06-27	pre-RA-sched: Cleanup register pressure tracking.	Andrew Trick
2011-06-27	Distinguish early clobber output operands from clobbered registers.	Jakob Stoklund Olesen
2011-06-24	The scheduler needs to be aware on the existence of untyped nodes when it per...	Owen Anderson
2011-06-24	Handle debug info for i128 constants.	Devang Patel
2011-06-22	Replace the existing forms of ConstantArray::get() with a single form	Jay Foad
2011-06-21	Fix some trailing issues from my introduction of MVT::untyped and its use for...	Owen Anderson
2011-06-21	Teach dag combine to match halfword byteswap patterns.	Evan Cheng
2011-06-20	Fix PromoteIntRes_TRUNCATE: Add support for cases where the	Nadav Rotem
2011-06-19	Code cleanups: Remove duplicated logic in PromotInteRes_BITCAST, reserve vect...	Nadav Rotem
2011-06-19	Calls to AssertZext and getZeroExtendInReg must be made using scalar types.	Nadav Rotem
2011-06-19	When promoting the vector elements in CopyToParts, use vector trunc	Nadav Rotem
2011-06-18	Don't allocate empty read-only SmallVectors during SelectionDAG deallocation.	Benjamin Kramer
2011-06-18	Remove unused but set variables.	Benjamin Kramer
2011-06-18	Fix UMULO support for 2x register width to allow the full	Eric Christopher
2011-06-17	Fix comment.	Eric Christopher
2011-06-17	Lower multiply with overflow checking to __mulo<mode>	Eric Christopher
2011-06-16	Don't use register classes larger than TLI->getRegClassFor(VT).	Jakob Stoklund Olesen
2011-06-16	Introduce MachineBranchProbabilityInfo class, which has similar API to	Jakub Staszak
2011-06-16	Change the REG_SEQUENCE SDNode to take an explict register class ID as its fi...	Owen Anderson
2011-06-16	Add TargetRegisterInfo::getRawAllocationOrder().	Jakob Stoklund Olesen
2011-06-16	Add a DAGCombine for (ext (binop (load x), cst)).	Nick Lewycky
2011-06-15	Add a new MVT::untyped. This will be used in future work for modelling ISA f...	Owen Anderson
2011-06-15	Added -stress-sched flag in the Asserts build.	Andrew Trick
2011-06-15	getZeroExtendInReg needs to get a scalar type	Nadav Rotem
2011-06-15	Enable the simplification of truncating-store after fixing the usage of	Nadav Rotem
2011-06-14	When pattern matching during instruction selection make sure shl x,1 is not	Chad Rosier
2011-06-14	Add a testcase for checking the integer-promotion of many different vector	Nadav Rotem
2011-06-14	Disable trunc-store simplification on vectors.	Nadav Rotem
2011-06-14	Add one more argument to the prefetch intrinsic to indicate whether it's a data	Bruno Cardoso Lopes
2011-06-13	Fix a bug in FindMemType. When widening vector loads, use a wider memory type	Nadav Rotem
2011-06-12	Fix a bug in the calculation of the vectorTypeBreakdown into registers. Odd	Nadav Rotem
2011-06-12	Improve the generated code by getCopyFromPartsVector for promoted integer types.	Nadav Rotem
2011-06-11	Revert r132871.	Chad Rosier
2011-06-11	Typo.	Chad Rosier
2011-06-10	80-col cleanups.	Eric Christopher
2011-06-09	Change this DAGCombine to build AND of SHR instead of SHR of AND; this matche...	Eli Friedman
2011-06-08	Add a parameter to CCState so that it can access the MachineFunction.	Eric Christopher
2011-06-08	Remove a temporary test case probe in CheckForLiveRegDef.	Andrew Trick
2011-06-07	Fix a merge bug in preRAsched for handling physreg aliases.	Andrew Trick
2011-06-06	Add methods to support the integer-promotion of vector types. Methods to	Nadav Rotem
2011-06-06	Avoid FGETSIGN of 80-bit types. Fixes PR10085.	Stuart Hastings
2011-06-06	PR10077: fix fast-isel of extractvalue of aggregate constants.	Eli Friedman
2011-06-04	TypeLegalizer: Add support for passing of vector-promoted types in registers ...	Nadav Rotem
2011-06-04	TypeLegalizer: Fix a bug in the promotion of elements of integer vectors.	Nadav Rotem
2011-06-03	Add a TODO about memory operands.	Eric Christopher
2011-06-02	Have LowerOperandForConstraint handle multiple character constraints.	Eric Christopher
2011-06-02	Revert 132424 to fix PR10068.	Rafael Espindola