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2008-05-12Merge from mainline.Tanya Lattner
Fix a missing break in the ISD::FLT_ROUNDS_ handling. git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_23@50989 91177308-0d34-0410-b5e6-96231b3b80d8
2008-05-07Turn StripPointerCast() into a methodAnton Korobeynikov
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50836 91177308-0d34-0410-b5e6-96231b3b80d8
2008-05-07Fix a bug in the ComputeMaskedBits logic for multiply.Dan Gohman
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50793 91177308-0d34-0410-b5e6-96231b3b80d8
2008-05-06Make StripPointerCast a common function (should we mak it method of Value ↵Anton Korobeynikov
instead?) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50775 91177308-0d34-0410-b5e6-96231b3b80d8
2008-05-06Make several variable declarations static.Dan Gohman
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50696 91177308-0d34-0410-b5e6-96231b3b80d8
2008-05-06Instead of enumerating each opcode that isn't handled thatDan Gohman
ComputeMaskedBits handles, just use a 'default:'. This avoids TargetLowering's list getting out of date with SelectionDAG's. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50693 91177308-0d34-0410-b5e6-96231b3b80d8
2008-05-06Correct the value of LowBits in srem and urem handling inDan Gohman
ComputeMaskedBits. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50692 91177308-0d34-0410-b5e6-96231b3b80d8
2008-05-05Added addition atomic instrinsics and, or, xor, min, and max.Mon P Wang
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50663 91177308-0d34-0410-b5e6-96231b3b80d8
2008-05-02Fix a mistake in the computation of leading zeros for udiv.Dan Gohman
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50591 91177308-0d34-0410-b5e6-96231b3b80d8
2008-05-02Fix a typo in a comment.Dan Gohman
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50562 91177308-0d34-0410-b5e6-96231b3b80d8
2008-05-02Use push_back(...) instead of resize(1, ...), per review feedback.Dan Gohman
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50561 91177308-0d34-0410-b5e6-96231b3b80d8
2008-05-01Fix uninitialized uses of the FPC variable.Dan Gohman
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50558 91177308-0d34-0410-b5e6-96231b3b80d8
2008-05-01don't randomly miscompile seto/setuo just because we are in Chris Lattner
ffastmath mode. This fixes rdar://5902801, a miscompilation of gcc.dg/builtins-8.c. Bill, please pull this into Tak. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50523 91177308-0d34-0410-b5e6-96231b3b80d8
2008-04-30Tail call optimization improvements:Arnold Schwaighofer
Move platform independent code (lowering of possibly overwritten arguments, check for tail call optimization eligibility) from target X86ISelectionLowering.cpp to TargetLowering.h and SelectionDAGISel.cpp. Initial PowerPC tail call implementation: Support ppc32 implemented and tested (passes my tests and test-suite llvm-test). Support ppc64 implemented and half tested (passes my tests). On ppc tail call optimization is performed if caller and callee are fastcc call is a tail call (in tail call position, call followed by ret) no variable argument lists or byval arguments option -tailcallopt is enabled Supported: * non pic tail calls on linux/darwin * module-local tail calls on linux(PIC/GOT)/darwin(PIC) * inter-module tail calls on darwin(PIC) If constraints are not met a normal call will be emitted. A test checking the argument lowering behaviour on x86-64 was added. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50477 91177308-0d34-0410-b5e6-96231b3b80d8
2008-04-30Fix custom target lowering for zero/any/sign_extend: make sure thatScott Michel
DAG.UpdateNodeOperands() is called before (not after) the call to TLI.LowerOperation(). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50461 91177308-0d34-0410-b5e6-96231b3b80d8
2008-04-29Use std::set instead of std::priority_queue for the RegReductionPriorityQueue. Roman Levenstein
This removes the existing bottleneck related to the removal of elements from the middle of the queue. Also fixes a subtle bug in ScheduleDAGRRList::CapturePred: It was updating the state of the SUnit before removing it. As a result, the comparison operators were working incorrectly and this SUnit could not be removed from the queue properly. Reviewed by Evan and Dan. Approved by Dan. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50412 91177308-0d34-0410-b5e6-96231b3b80d8
2008-04-29make the vector conversion magic handle multiple results.Chris Lattner
We now compile test2/test3 to: _test2: ## InlineAsm Start set %xmm0, %xmm1 ## InlineAsm End addps %xmm1, %xmm0 ret _test3: ## InlineAsm Start set %xmm0, %xmm1 ## InlineAsm End paddd %xmm1, %xmm0 ret as expected. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50389 91177308-0d34-0410-b5e6-96231b3b80d8
2008-04-29add support for multiple return values in inline asm. This is a step Chris Lattner
towards PR2094. It now compiles the attached .ll file to: _sad16_sse2: movslq %ecx, %rax ## InlineAsm Start %ecx %rdx %rax %rax %r8d %rdx %rsi ## InlineAsm End ## InlineAsm Start set %eax ## InlineAsm End ret which is pretty decent for a 3 output, 4 input asm. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50386 91177308-0d34-0410-b5e6-96231b3b80d8
2008-04-28Fix a bug in RegsForValue::getCopyToRegs() that causes cyclical scheduling ↵Evan Cheng
units. If it's creating multiple CopyToReg nodes that are "flagged" together, it should not create a TokenFactor for it's chain outputs: c1, f1 = CopyToReg c2, f2 = CopyToReg c3 = TokenFactor c1, c2 ... = user c3, ..., f2 Now that the two CopyToReg's and the user are "flagged" together. They effectively forms a single scheduling unit. The TokenFactor is now both an operand and a successor of the Flagged nodes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50376 91177308-0d34-0410-b5e6-96231b3b80d8
2008-04-28Evan pointed out that folding sext to zext may not be correctDan Gohman
if the zext is not legal. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50368 91177308-0d34-0410-b5e6-96231b3b80d8
2008-04-28Delete an unused constructor.Dan Gohman
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50367 91177308-0d34-0410-b5e6-96231b3b80d8
2008-04-28Add a comment to CreateRegForValue that clarifies the handling ofDan Gohman
aggregate types. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50366 91177308-0d34-0410-b5e6-96231b3b80d8
2008-04-28Rewrite the comments for RegsForValue and its members, andDan Gohman
reorder some of the members for clarity. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50365 91177308-0d34-0410-b5e6-96231b3b80d8
2008-04-28Don't call size() on each iteration of the loop.Dan Gohman
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50361 91177308-0d34-0410-b5e6-96231b3b80d8
2008-04-28Fix the SVOffset values for loads and stores produced byDan Gohman
memcpy/memset expansion. It was a bug for the SVOffset value to be used in the actual address calculations. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50359 91177308-0d34-0410-b5e6-96231b3b80d8
2008-04-28Teach InstCombine's ComputeMaskedBits what SelectionDAG'sDan Gohman
ComputeMaskedBits knows about cttz, ctlz, and ctpop. Teach SelectionDAG's ComputeMaskedBits what InstCombine's knows about SRem. And teach them both some things about high bits in Mul, UDiv, URem, and Sub. This allows instcombine and dagcombine to eliminate sign-extension operations in several new cases. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50358 91177308-0d34-0410-b5e6-96231b3b80d8
2008-04-28Teach DAGCombine to convert (sext x) to (zext x) when theDan Gohman
sign-bit of x is known to be zero. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50357 91177308-0d34-0410-b5e6-96231b3b80d8
2008-04-28Another collection of random cleanups. No functionality change.Chris Lattner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50341 91177308-0d34-0410-b5e6-96231b3b80d8
2008-04-28Remove the SmallVector ctor that converts from a SmallVectorImpl. ThisChris Lattner
conversion open the door for many nasty implicit conversion issues, and can be easily solved by initializing with (V.begin(), V.end()) when needed. This patch includes many small cleanups for sdisel also. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50340 91177308-0d34-0410-b5e6-96231b3b80d8
2008-04-28switch RegsForValue::Regs to be a SmallVector to avoidChris Lattner
heap thrash on tiny (usually single-element) vectors. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50335 91177308-0d34-0410-b5e6-96231b3b80d8
2008-04-27move static function out of anon namespace, no functionality change.Chris Lattner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50330 91177308-0d34-0410-b5e6-96231b3b80d8
2008-04-27Another step to getting multiple result inline asm to work.Chris Lattner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50329 91177308-0d34-0410-b5e6-96231b3b80d8
2008-04-27typoChris Lattner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50316 91177308-0d34-0410-b5e6-96231b3b80d8
2008-04-27Implement a signficant optimization for inline asm:Chris Lattner
When choosing between constraints with multiple options, like "ir", test to see if we can use the 'i' constraint and go with that if possible. This produces more optimal ASM in all cases (sparing a register and an instruction to load it), and fixes inline asm like this: void test () { asm volatile (" %c0 %1 " : : "imr" (42), "imr"(14)); } Previously we would dump "42" into a memory location (which is ok for the 'm' constraint) which would cause a problem because the 'c' modifier is not valid on memory operands. Isn't it great how inline asm turns 'missed optimization' into 'compile failed'?? Incidentally, this was the todo in PowerPC/2007-04-24-InlineAsm-I-Modifier.ll Please do NOT pull this into Tak. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50315 91177308-0d34-0410-b5e6-96231b3b80d8
2008-04-27isa+cast -> dyn_castChris Lattner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50314 91177308-0d34-0410-b5e6-96231b3b80d8
2008-04-27Move a bunch of inline asm code out of line.Chris Lattner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50313 91177308-0d34-0410-b5e6-96231b3b80d8
2008-04-26A few inline asm cleanups:Chris Lattner
- Make targetlowering.h fit in 80 cols. - Make LowerAsmOperandForConstraint const. - Make lowerXConstraint -> LowerXConstraint - Make LowerXConstraint return a const char* instead of taking a string byref. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50312 91177308-0d34-0410-b5e6-96231b3b80d8
2008-04-25Remove the code from CodeGenPrepare that moved getresult instructionsDan Gohman
to the block that defines their operands. This doesn't work in the case that the operand is an invoke, because invoke is a terminator and must be the last instruction in a block. Replace it with support in SelectionDAGISel for copying struct values into sequences of virtual registers. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50279 91177308-0d34-0410-b5e6-96231b3b80d8
2008-04-25Pull the code to perform an INSERT_VECTOR_ELT in memory out into its own Nate Begeman
function, and then use it to fix a bug in SplitVectorOp that expected inserts to always have constant insertion indices. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50273 91177308-0d34-0410-b5e6-96231b3b80d8
2008-04-23Use isa instead of dyn_cast.Dan Gohman
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50181 91177308-0d34-0410-b5e6-96231b3b80d8
2008-04-23Add support to codegen for getresult instructions with undef operands.Dan Gohman
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50180 91177308-0d34-0410-b5e6-96231b3b80d8
2008-04-21Fix an out-of-bounds access in -view-sunit-dags in the case of anDan Gohman
empty ScheduleDAG. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50054 91177308-0d34-0410-b5e6-96231b3b80d8
2008-04-20Check we aren't trying to convert PPC long double.Dale Johannesen
This fixes the testsuite failure on ppcf128-4.ll. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@49994 91177308-0d34-0410-b5e6-96231b3b80d8
2008-04-20Switch to using Simplified ConstantFP::get API.Chris Lattner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@49977 91177308-0d34-0410-b5e6-96231b3b80d8
2008-04-18Implement a bit more softfloat support inDuncan Sands
LegalizeTypes. Correct the load logic so that it actually works, and also teach it to handle floating point extending loads. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@49923 91177308-0d34-0410-b5e6-96231b3b80d8
2008-04-18Add some more FIXME's for indexed loads and stores.Duncan Sands
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@49916 91177308-0d34-0410-b5e6-96231b3b80d8
2008-04-18Provide an explicit list of operands to MakeLibcall,Duncan Sands
rather than having it suck them out of a node. Add a bunch of new libcalls, and remove dead softfloat code (dead, because FloatToInt is used not Expand in this case). Note that indexed stores probably aren't handled properly, likewise for loads. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@49915 91177308-0d34-0410-b5e6-96231b3b80d8
2008-04-17Remove the implicit conversion from SDOperandPtr to SDOperand*; thisDan Gohman
may fix a build error on Visual Studio. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@49876 91177308-0d34-0410-b5e6-96231b3b80d8
2008-04-17Correct the SrcValue information in the Expand code for va_copy.Dan Gohman
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@49839 91177308-0d34-0410-b5e6-96231b3b80d8
2008-04-16Ongoing work on improving the instruction selection infrastructure:Roman Levenstein
Rename SDOperandImpl back to SDOperand. Introduce the SDUse class that represents a use of the SDNode referred by an SDOperand. Now it is more similar to Use/Value classes. Patch is approved by Dan Gohman. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@49795 91177308-0d34-0410-b5e6-96231b3b80d8
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