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path: root/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
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2006-03-13Handle the removal of the debug chain.Jim Laskey
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26729 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-10Added a parameter to control whether Constant::getStringValue() would chopEvan Cheng
off the result string at the first null terminator. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26704 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-10scrape out bits of llvm-dbChris Lattner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26701 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-10Simplify the interface to the schedulers, to not pass the selected heuristicin.Chris Lattner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26692 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-09remove dbg_declare, it's not used yet.Chris Lattner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26659 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-08Get rid of the multiple copies of getStringValue. Now a Constant:: method.Jim Laskey
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26616 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-08Change the interface for getting a target HazardRecognizer to be more clean.Chris Lattner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26608 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-06Hoist the HazardRecognizer out of the ScheduleDAGList.cpp file to whereChris Lattner
targets can implement them. Make the top-down scheduler non-g5-specific. Remove the old testing hazard recognizer. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26569 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-05Split the list scheduler into top-down and bottom-up pieces. The priorityChris Lattner
function of the top-down scheduler are completely bogus currently, and having (future) PPC specific in this file is also wrong, but this is a small incremental step. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26552 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-05Codegen copysign[f] into a FCOPYSIGN nodeChris Lattner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26542 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-03Add more vector NodeTypes: VSDIV, VUDIV, VAND, VOR, and VXOR.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26504 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-03remove the read/write port/io intrinsics.Chris Lattner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26479 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-03Split memcpy/memset/memmove intrinsics into i32/i64 versions, resolvingChris Lattner
PR709, and paving the way for future progress. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26476 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-01Vector ops lowering.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26436 91177308-0d34-0410-b5e6-96231b3b80d8
2006-02-27Add support for output memory constraints.Chris Lattner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26410 91177308-0d34-0410-b5e6-96231b3b80d8
2006-02-24Get VC++ building again.Jeff Cohen
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26351 91177308-0d34-0410-b5e6-96231b3b80d8
2006-02-24Implement (most of) selection of inline asm memory operands.Chris Lattner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26350 91177308-0d34-0410-b5e6-96231b3b80d8
2006-02-24Lower C_Memory operands.Chris Lattner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26346 91177308-0d34-0410-b5e6-96231b3b80d8
2006-02-23Fix an endianness problem on big-endian targets with expanded operandsChris Lattner
to inline asms. Mark some methods const. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26334 91177308-0d34-0410-b5e6-96231b3b80d8
2006-02-23Record all of the expanded registers in the DAG and machine instr, fixingChris Lattner
several bugs in inline asm expanded operands. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26332 91177308-0d34-0410-b5e6-96231b3b80d8
2006-02-22This fixes a couple of problems with expansionChris Lattner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26318 91177308-0d34-0410-b5e6-96231b3b80d8
2006-02-22Change a whole bunch of code to be built around RegsForValue instead ofChris Lattner
a single register number. This fully implements promotion for inline asms, expand is close but not quite right yet. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26316 91177308-0d34-0410-b5e6-96231b3b80d8
2006-02-22split register class handling from explicit physreg handling.Chris Lattner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26308 91177308-0d34-0410-b5e6-96231b3b80d8
2006-02-21Adjust to changes in getRegForInlineAsmConstraint prototypeChris Lattner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26306 91177308-0d34-0410-b5e6-96231b3b80d8
2006-02-16Dumb bug. Code sees a memcpy from X+c so it increments src offset. But itEvan Cheng
turns out not to point to a constant string but it forgot change the offset back. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26242 91177308-0d34-0410-b5e6-96231b3b80d8
2006-02-16If the false case is the current basic block, then this is a self loop.Evan Cheng
We do not want to emit "Loop: ... brcond Out; br Loop", as it adds an extra instruction in the loop. Instead, invert the condition and emit "Loop: ... br!cond Loop; br Out. Generalize the fix by moving it from PPCDAGToDAGISel to SelectionDAGLowering. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26231 91177308-0d34-0410-b5e6-96231b3b80d8
2006-02-15Remove an unused function parameter.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26221 91177308-0d34-0410-b5e6-96231b3b80d8
2006-02-15Turn a memcpy from string constant into a series of stores of constant values.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26219 91177308-0d34-0410-b5e6-96231b3b80d8
2006-02-15Lower memcpy with small constant size operand into a series of load / storeEvan Cheng
ops. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26195 91177308-0d34-0410-b5e6-96231b3b80d8
2006-02-14Doh again!Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26188 91177308-0d34-0410-b5e6-96231b3b80d8
2006-02-14Keep to < 80 colsEvan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26177 91177308-0d34-0410-b5e6-96231b3b80d8
2006-02-14Missed a break so memcpy cases fell through to memset. Doh.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26176 91177308-0d34-0410-b5e6-96231b3b80d8
2006-02-14Fixed a build breakage.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26175 91177308-0d34-0410-b5e6-96231b3b80d8
2006-02-14Rename maxStoresPerMemSet to maxStoresPerMemset, etc.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26174 91177308-0d34-0410-b5e6-96231b3b80d8
2006-02-14Expand memset dst, c, size to a series of stores if size falls below theEvan Cheng
target specific theshold, e.g. 16 for x86. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26171 91177308-0d34-0410-b5e6-96231b3b80d8
2006-02-14now that libcalls don't suck, we can remove this hackChris Lattner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26164 91177308-0d34-0410-b5e6-96231b3b80d8
2006-02-13Rename to better reflect usage (current and planned.)Jim Laskey
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26145 91177308-0d34-0410-b5e6-96231b3b80d8
2006-02-11Reorg for integration with gcc4. Old style debug info will not be passed thoughJim Laskey
to SelIDAG. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26115 91177308-0d34-0410-b5e6-96231b3b80d8
2006-02-04Get rid of some memory leaks identified by ValgrindEvan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25960 91177308-0d34-0410-b5e6-96231b3b80d8
2006-02-04Add initial support for immediates. This allows us to compile this:Chris Lattner
int %rlwnm(int %A, int %B) { %C = call int asm "rlwnm $0, $1, $2, $3, $4", "=r,r,r,n,n"(int %A, int %B, int 4, int 17) ret int %C } into: _rlwnm: or r2, r3, r3 or r3, r4, r4 rlwnm r2, r2, r3, 4, 17 ;; note the immediates :) or r3, r2, r2 blr git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25955 91177308-0d34-0410-b5e6-96231b3b80d8
2006-02-04Initial early support for non-register operands, like immediatesChris Lattner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25952 91177308-0d34-0410-b5e6-96231b3b80d8
2006-02-03remove some #ifdef'd out code, which should properly be in the dag combiner ↵Chris Lattner
anyway. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25941 91177308-0d34-0410-b5e6-96231b3b80d8
2006-02-02Implement matching constraints. We can now say things like this:Chris Lattner
%C = call int asm "xyz $0, $1, $2, $3", "=r,r,r,0"(int %A, int %B, int 4) and get: xyz r2, r3, r4, r2 note that the r2's are pinned together. Yaay for 2-address instructions. 2342 ---------------------------------------------------------------------- git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25893 91177308-0d34-0410-b5e6-96231b3b80d8
2006-02-01Implement simple register assignment for inline asms. This allows us to ↵Chris Lattner
compile: int %test(int %A, int %B) { %C = call int asm "xyz $0, $1, $2", "=r,r,r"(int %A, int %B) ret int %C } into: (0x8906130, LLVM BB @0x8902220): %r2 = OR4 %r3, %r3 %r3 = OR4 %r4, %r4 INLINEASM <es:xyz $0, $1, $2>, %r2<def>, %r2, %r3 %r3 = OR4 %r2, %r2 BLR which asmprints as: _test: or r2, r3, r3 or r3, r4, r4 xyz $0, $1, $2 ;; need to print the operands now :) or r3, r2, r2 blr git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25878 91177308-0d34-0410-b5e6-96231b3b80d8
2006-02-01adjust to changes in InlineAsm interface. Fix a few minor bugs.Chris Lattner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25865 91177308-0d34-0410-b5e6-96231b3b80d8
2006-01-31Handle physreg input/outputs. We now compile this:Chris Lattner
int %test_cpuid(int %op) { %B = alloca int %C = alloca int %D = alloca int %A = call int asm "cpuid", "=eax,==ebx,==ecx,==edx,eax"(int* %B, int* %C, int* %D, int %op) %Bv = load int* %B %Cv = load int* %C %Dv = load int* %D %x = add int %A, %Bv %y = add int %x, %Cv %z = add int %y, %Dv ret int %z } to this: _test_cpuid: sub %ESP, 16 mov DWORD PTR [%ESP], %EBX mov %EAX, DWORD PTR [%ESP + 20] cpuid mov DWORD PTR [%ESP + 8], %ECX mov DWORD PTR [%ESP + 12], %EBX mov DWORD PTR [%ESP + 4], %EDX mov %ECX, DWORD PTR [%ESP + 12] add %EAX, %ECX mov %ECX, DWORD PTR [%ESP + 8] add %EAX, %ECX mov %ECX, DWORD PTR [%ESP + 4] add %EAX, %ECX mov %EBX, DWORD PTR [%ESP] add %ESP, 16 ret ... note the proper register allocation. :) it is unclear to me why the loads aren't folded into the adds. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25827 91177308-0d34-0410-b5e6-96231b3b80d8
2006-01-28remove method I just addedChris Lattner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25728 91177308-0d34-0410-b5e6-96231b3b80d8
2006-01-28add a new callbackChris Lattner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25727 91177308-0d34-0410-b5e6-96231b3b80d8
2006-01-28Implement Promote for VAARG, and allow it to be custom promoted for peopleNate Begeman
who don't want the default behavior (Alpha). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25726 91177308-0d34-0410-b5e6-96231b3b80d8
2006-01-27Remove TLI.LowerReturnTo, and just let targets custom lower ISD::RET forNate Begeman
the same functionality. This addresses another piece of bug 680. Next, on to fixing Alpha VAARG, which I broke last time. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25696 91177308-0d34-0410-b5e6-96231b3b80d8
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