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path: root/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
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2011-07-29Do not lose branch weights when lowering SwitchInst.Jakub Staszak
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136529 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-29Remove unneeded const_cast.Jakub Staszak
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136506 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-29Misc optimizer+codegen work for 'cmpxchg' and 'atomicrmw'. They appear to beEli Friedman
working on x86 (at least for trivial testcases); other architectures will need more work so that they actually emit the appropriate instructions for orderings stricter than 'monotonic'. (As far as I can tell, the ARM, PPC, Mips, and Alpha backends need such changes.) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136457 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-29Use the pointer type size.Bill Wendling
With this, we can now compile a simple EH program. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136446 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-29And now something that compiles...Bill Wendling
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136445 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-29Make sure to sext or trunc the result from the register.Bill Wendling
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136444 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-28Visit the landingpad instruction.Bill Wendling
This generates the correct SDNodes for the landingpad instruction. It makes an assumption that the result of the landingpad instruction has at least two values. And that the first value is a pointer to the exception object and the second value is the "selector." git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136430 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-28LangRef and basic memory-representation/reading/writing for 'cmpxchg' andEli Friedman
'atomicrmw' instructions, which allow representing all the current atomic rmw intrinsics. The allowed operands for these instructions are heavily restricted at the moment; we can probably loosen it a bit, but supporting general first-class types (where it makes sense) might get a bit complicated, given how SelectionDAG works. As an initial cut, these operations do not support specifying an alignment, but it would be possible to add if we think it's useful. Specifying an alignment lower than the natural alignment would be essentially impossible to support on anything other than x86, but specifying a greater alignment would be possible. I can't think of any useful optimizations which would use that information, but maybe someone else has ideas. Optimizer/codegen support coming soon. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136404 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-28The personality function should be a Function* and not just a Value*.Bill Wendling
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136392 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-27Code generation for 'fence' instruction.Eli Friedman
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136283 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-27Merge the contents from exception-handling-rewrite to the mainline.Bill Wendling
This adds the new instructions 'landingpad' and 'resume'. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136253 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-27Explicitly cast narrowing conversions inside {}s that will become errors inJeffrey Yasskin
C++0x. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136211 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-25Initial implementation of 'fence' instruction, the new C++0x-style ↵Eli Friedman
replacement for llvm.memory.barrier. This is just a LangRef entry and reading/writing/memory representation; optimizer+codegen support coming soon. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136009 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-18land David Blaikie's patch to de-constify Type, with a few tweaks.Chris Lattner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135375 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-14Check register class matching instead of width of type matchingEric Christopher
when determining validity of matching constraint. Allow i1 types access to the GR8 reg class for x86. Fixes PR10352 and rdar://9777108 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135180 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-14Don't emit a bit test if there is only one case the test can yield false. A ↵Benjamin Kramer
simple SETNE is sufficient. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135126 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-13Convert InsertValueInst and ExtractValueInst APIs to use ArrayRef.Jay Foad
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135040 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-08Add an intrinsic and codegen support for fused multiply-accumulate. The intentCameron Zwarich
is to use this for architectures that have a native FMA instruction. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134742 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-08Apparently we can't expect a BinaryOperator here.Benjamin Kramer
Should fix llvm-gcc selfhost. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134699 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-08Emit a more efficient magic number multiplication for exact sdivs.Benjamin Kramer
We have to do this in DAGBuilder instead of DAGCombiner, because the exact bit is lost after building. struct foo { char x[24]; }; long bar(struct foo *a, struct foo *b) { return a-b; } is now compiled into movl 4(%esp), %eax subl 8(%esp), %eax sarl $3, %eax imull $-1431655765, %eax, %eax instead of movl 4(%esp), %eax subl 8(%esp), %eax movl $715827883, %ecx imull %ecx movl %edx, %eax shrl $31, %eax sarl $2, %edx addl %eax, %edx movl %edx, %eax git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134695 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-06Introduce "expect" intrinsic instructions.Jakub Staszak
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134516 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-30Remove getRegClassForInlineAsmConstraint and all dependencies.Eric Christopher
Fixes rdar://9643582 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134123 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-27Distinguish early clobber output operands from clobbered registers.Jakob Stoklund Olesen
Both become <earlyclobber> defs on the INLINEASM MachineInstr, but we now use two different asm operand kinds. The new Kind_Clobber is treated identically to the old Kind_RegDefEarlyClobber for now, but x87 floating point stack inline assembly does care about the difference. This will pop a register off the stack: asm("fstp %st" : : "t"(x) : "st"); While this will pop the input and push an output: asm("fst %st" : "=&t"(r) : "t"(x)); We need to know if ST0 was a clobber or an output operand, and we can't depend on <dead> flags for that. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133902 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-19When promoting the vector elements in CopyToParts, use vector truncNadav Rotem
instead of scalarizing, and doing an element-by-element truncat. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133382 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-16Introduce MachineBranchProbabilityInfo class, which has similar API toJakub Staszak
BranchProbabilityInfo (expect setEdgeWeight which is not available here). Branch Weights are kept in MachineBasicBlocks. To turn off this analysis set -use-mbpi=false. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133184 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-16Add TargetRegisterInfo::getRawAllocationOrder().Jakob Stoklund Olesen
This virtual function will replace allocation_order_begin/end as the one to override when implementing custom allocation orders. It is simpler to have one function return an ArrayRef than having two virtual functions computing different ends of the same array. Use getRawAllocationOrder() in place of allocation_order_begin() where it makes sense, but leave some clients that look like they really want the filtered allocation orders from RegisterClassInfo. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133170 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-14Add one more argument to the prefetch intrinsic to indicate whether it's a dataBruno Cardoso Lopes
or instruction cache access. Update the targets to match it and also teach autoupgrade. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132976 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-12Improve the generated code by getCopyFromPartsVector for promoted integer types.Nadav Rotem
Instead of scalarizing, and doing an element-by-element truncat, use vector truncate. Add support for scalarization of vectors: i8 -> <1 x i1> (from Duncan's testcase). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132892 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-08Add a parameter to CCState so that it can access the MachineFunction.Eric Christopher
No functional change. Part of PR6965 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132763 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-04TypeLegalizer: Add support for passing of vector-promoted types in registers ↵Nadav Rotem
(copyFromParts/copyToParts). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132649 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-03Add a TODO about memory operands.Eric Christopher
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132559 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-02Have LowerOperandForConstraint handle multiple character constraints.Eric Christopher
Part of rdar://9119939 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132510 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-01Allow bitcasts between valid types of the same size and vectorEric Christopher
types if the vector type is legal. Fixes rdar://9306086 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132420 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-23Preserve debug info during iSel by keeping DanglingDebugInfoMap live until ↵Devang Patel
end of function. Patch by Micah Villmow git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131908 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-22Eliminate some temporary variables, and don't call getByValTypeAlignmentChris Lattner
when we're just going to throw the result away. No functionality change. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131880 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-16Preserve debug info for unused zero extended boolean argument.Devang Patel
Radar 9422775. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131422 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-13Make codegen able to handle values of empty types. This is one wayRafael Espindola
to fix PR9900. I will keep it open until sable is able to comment on it. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131294 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-11Give the 'eh.sjlj.dispatchsetup' intrinsic call the value coming from the setjmpBill Wendling
intrinsic call. This prevents it from being reordered so that it appears *before* the setjmp intrinsic (thus making it completely useless). <rdar://problem/9409683> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131174 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-10Disable my little CopyToReg argument hack with fast-isel. ↵Eli Friedman
rdar://problem/9413587 . git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131156 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-09Look through struct wrapped types for inline asm statments.Eric Christopher
Patch by Evan Cheng. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131093 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-0680 col violations.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131015 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-05Avoid extra vreg copies for arguments passed in registers. Specifically, ↵Eli Friedman
this can make MachineCSE more effective in some cases (especially in small functions). PR8361 / part of rdar://problem/8259436 . git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130928 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-25A dbg.declare may not be in entry block, even if it is referring to an ↵Devang Patel
incoming argument. However, It is appropriate to emit DBG_VALUE referring to this incoming argument in entry block in MachineFunction. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130129 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-15Fix a ton of comment typos found by codespell. Patch byChris Lattner
Luis Felipe Strano Moraes! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129558 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-09Avoid excess precision issues that lead to generating host-compiler-specific ↵Chris Lattner
code. Switch lowering probably shouldn't be using FP for this. This resolves PR9581. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129199 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-08Change -arm-trap-func= into a non-arm specific option. Now Intrinsic::trap ↵Evan Cheng
is lowered into a call to the specified trap function at sdisel time. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129152 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-05Revamp the SjLj "dispatch setup" intrinsic.Bill Wendling
It needed to be moved closer to the setjmp statement, because the code directly after the setjmp needs to know about values that are on the stack. Also, the 'bitcast' of the function context was causing a dead load. This wouldn't be too horrible, except that at -O0 it wasn't optimized out, and because it wasn't using the correct base pointer (if there is a VLA), it would try to access a value from a garbage address. <rdar://problem/9130540> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128873 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-01Add comments.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128730 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-01Assign node order numbers to results of call instruction lowering. This ↵Evan Cheng
should improve src line debug info when sdisel is used. rdar://9199118 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128728 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-26Turn SelectionDAGBuilder::GetRegistersForValue into a local function.Benjamin Kramer
It couldn't be used outside of the file because SDISelAsmOperandInfo is local to SelectionDAGBuilder.cpp. Making it a static function avoids a weird linkage dance. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128342 91177308-0d34-0410-b5e6-96231b3b80d8
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