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implements CodeGen/PowerPC/div-2.ll
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with the dag combiner. This speeds up espresso by 8%, reaching performance
parity with the dag-combiner-disabled llc.
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dead node elim and dag combiner passes where the root is potentially updated.
This fixes a fixme in the dag combiner.
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Though I have done extensive testing, it is possible that this will break
things in configs I can't test. Please let me know if this causes a problem
and I'll fix it ASAP.
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This happens all the time on PPC for bool values, e.g. eliminating a xori
in inverted-bool-compares.ll.
This should be added to the dag combiner as well.
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select (x < y), 1, 0 -> (x < y) incorrectly: the setcc returns i1 but the
select returned i32. Add the zero extend as needed.
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as setcc and select next.
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as well as fixing how we replace old values with new values.
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we were losing a node, causing an assertion to fail. Now we eagerly delete
discovered CSE's, and provide an optional vector to keep track of these
discovered equivalences.
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from the binary ops map, even if they had multiple results. This latent bug
caused a few failures with the dag isel last night.
To prevent stuff like this from happening in the future, add some really
strict checking to make sure that the CSE maps always match up with reality!
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over to DAGCombiner.cpp
1. Don't assume that SetCC returns i1 when folding (xor (setcc) constant)
2. Don't duplicate code in folding AND with AssertZext that is handled by
MaskedValueIsZero
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case in MaskedValueIsZero was wrong.
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MaskedValueIsZero.
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likethis, it is a requirement on PPC, which can have an f32 value in r3 at onepoint in a function and a f64 value in r3 at another point. :(
This fixes compilation of mesa
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them. This allows for elminination of redundant extends in the entry
blocks of functions on PowerPC.
Add support for i32 x i32 -> i64 multiplies, by recognizing when the inputs
to ISD::MUL in ExpandOp are actually just extended i32 values and not real
i64 values. this allows us to codegen
int mulhs(int a, int b) { return ((long long)a * b) >> 32; }
as:
_mulhs:
mulhw r3, r4, r3
blr
instead of:
_mulhs:
mulhwu r2, r4, r3
srawi r5, r3, 31
mullw r5, r4, r5
add r2, r2, r5
srawi r4, r4, 31
mullw r3, r4, r3
add r3, r2, r3
blr
with a similar improvement on x86.
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register class.
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putting it into the constant pool. This allows the isel machinery to
create constants that it will end up deciding are not needed, without them
ending up in the resultant function constant pool.
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every other SD API. Fix it to take the opcode before the types.
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Add some foldings to hopefully help the illegal setcc issue, and move some code around.
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select. Also teach it that the bit count instructions can only set the low bits
of the result, depending on the size of the input.
This allows us to compile this:
int %eq0(int %a) {
%tmp.1 = seteq int %a, 0 ; <bool> [#uses=1]
%tmp.2 = cast bool %tmp.1 to int ; <int> [#uses=1]
ret int %tmp.2
}
To this:
_eq0:
cntlzw r2, r3
srwi r3, r2, 5
blr
instead of this:
_eq0:
cntlzw r2, r3
rlwinm r3, r2, 27, 31, 31
blr
when setcc is marked illegal on ppc (which restores parity to non-illegal
setcc). Thanks to Nate for pointing this out.
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nodes so that backends don't have to.
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either seteq X, 0 or srl (ctlz X), size(X-1), depending on what's legal
for the target.
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