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path: root/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp
AgeCommit message (Expand)Author
2011-03-05Fix for -sched-high-latency-cycles in sched=list-ilp mode.Andrew Trick
2011-03-05Increased the register pressure limit on x86_64 from 8 to 12Andrew Trick
2011-02-04Introducing a new method of tracking register pressure. We can'tAndrew Trick
2011-02-03whitespaceAndrew Trick
2011-01-27Reapply 124301Devang Patel
2011-01-26Revert 124301.Devang Patel
2011-01-26Process valid SDDbgValues even if the node does not have any order assigned.Devang Patel
2011-01-26Refactor.Devang Patel
2011-01-25This assertion is too restrictive, it does not apply for dangling dbg value n...Devang Patel
2010-12-23flags -> glue for selectiondagChris Lattner
2010-12-21rename MVT::Flag to MVT::Glue. "Flag" is a terrible name forChris Lattner
2010-11-03Two sets of changes. Sorry they are intermingled.Evan Cheng
2010-10-29Avoiding overly aggressive latency scheduling. If the two nodes share anEvan Cheng
2010-10-28Re-commit 117518 and 117519 now that ARM MC test failures are out of the way.Evan Cheng
2010-10-28Revert 117518 and 117519 for now. They changed scheduling and cause MC tests ...Evan Cheng
2010-10-28Fix a major bug in operand latency computation. The use index must be adjustedEvan Cheng
2010-10-06- Add TargetInstrInfo::getOperandLatency() to compute operand latencies. ThisEvan Cheng
2010-09-29Model Cortex-a9 load to SUB, RSB, ADD, ADC, SBC, RSC, CMN, MVN, or CMPEvan Cheng
2010-09-10Teach if-converter to be more careful with predicating instructions that wouldEvan Cheng
2010-08-10Add missing null check reported by Amaury Pouly.Evan Cheng
2010-07-10Fix a bug in the code which re-inserts DBG_VALUE nodes after scheduling;Dan Gohman
2010-07-10Reapply bottom-up fast-isel, with several fixes for x86-32:Dan Gohman
2010-07-09--- Reverse-merging r107947 into '.':Bob Wilson
2010-07-09Re-apply bottom-up fast-isel, with fixes. Be very careful to avoid emittingDan Gohman
2010-06-30grammar tweak in comment.Jim Grosbach
2010-06-29Add a VT argument to getMinimalPhysRegClass and replace the copy related usesRafael Espindola
2010-06-25Remove variables which are assigned to but for which the valueDuncan Sands
2010-06-24It's possible that a flag is added to the SDNode that points back to theBill Wendling
2010-06-23MorphNodeTo doesn't preserve the memory operands. Because we're morphing a nodeBill Wendling
2010-06-21Use A.append(...) instead of A.insert(A.end(), ...) when A is aDan Gohman
2010-06-10Code refactoring, no functionality changes.Evan Cheng
2010-05-28Fix some latency computation bugs: if the use is not a machine opcode do not ...Evan Cheng
2010-05-20Allow targets more controls on what nodes are scheduled by reg pressure, what...Evan Cheng
2010-05-20Add a hybrid bottom up scheduler that reduce register usage while avoidingEvan Cheng
2010-05-19Code clean up.Evan Cheng
2010-05-01Get rid of the EdgeMapping map. Instead, just check for BasicBlockDan Gohman
2010-04-30EmitDbgValue doesn't need its EdgeMapping argument.Dan Gohman
2010-04-26Add DBG_VALUE handling for byval parameters; thisDale Johannesen
2010-04-26- Move TargetLowering::EmitTargetCodeForFrameDebugValue to TargetInstrInfo an...Evan Cheng
2010-04-17Fix -Wcast-qual warnings.Dan Gohman
2010-03-25Scheduler assumes SDDbgValue nodes are in source order. That's true currently...Evan Cheng
2010-03-25Remove a fixme that doesn't make sense any more.Evan Cheng
2010-03-25Change how dbg_value sdnodes are converted into machine instructions. Their p...Evan Cheng
2010-03-14Rename SDDbgValue.h to SDNodeDbgValue.h for consistency.Evan Cheng
2010-03-10Progress towards shepherding debug info through SelectionDAG.Dale Johannesen
2010-02-24Change the scheduler from adding nodes in allnodes orderChris Lattner
2010-01-22Enable pre-regalloc scheduling load clustering by default.Evan Cheng
2010-01-22Teach pre-regalloc scheduler to schedule loads from nearby addresses. It may ...Evan Cheng
2010-01-05Change errs() to dbgs().David Greene
2009-12-18Changes from review:Bill Wendling