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Age	Commit message (Expand)	Author
2011-06-27	More refactoring. Move getRegClass from TargetOperandInfo to TargetInstrInfo.	Evan Cheng
2011-06-27	pre-RA-sched: Cleanup register pressure tracking.	Andrew Trick
2011-06-27	Distinguish early clobber output operands from clobbered registers.	Jakob Stoklund Olesen
2011-06-21	Fix some trailing issues from my introduction of MVT::untyped and its use for...	Owen Anderson
2011-06-18	Remove unused but set variables.	Benjamin Kramer
2011-06-15	Add a new MVT::untyped. This will be used in future work for modelling ISA f...	Owen Anderson
2011-06-15	Added -stress-sched flag in the Asserts build.	Andrew Trick
2011-06-08	Remove a temporary test case probe in CheckForLiveRegDef.	Andrew Trick
2011-06-07	Fix a merge bug in preRAsched for handling physreg aliases.	Andrew Trick
2011-04-26	Be careful about scheduling nodes above previous calls. It increase usages of	Evan Cheng
2011-04-26	Fix typo	Evan Cheng
2011-04-14	In the pre-RA scheduler, maintain cmp+br proximity.	Andrew Trick
2011-04-13	Recommit r129383. PreRA scheduler heuristic fixes: VRegCycle, TokenFactor lat...	Andrew Trick
2011-04-12	Revert 129383. It causes some targets to hit a scheduler assert.	Andrew Trick
2011-04-12	PreRA scheduler heuristic fixes: VRegCycle, TokenFactor latency.	Andrew Trick
2011-04-07	Added a check in the preRA scheduler for potential interference on a	Andrew Trick
2011-03-25	Fix for -pre-RA-sched=source.	Andrew Trick
2011-03-23	Ensure that def-side physreg copies are scheduled above any other uses	Andrew Trick
2011-03-23	whitespace	Andrew Trick
2011-03-21	Grammar-o.	Eric Christopher
2011-03-10	Re-commit 127368 and 127371. They are exonerated.	Evan Cheng
2011-03-09	Revert 127368 and 127371 for now.	Evan Cheng
2011-03-09	Change the definition of TargetRegisterInfo::getCrossCopyRegClass to be more	Evan Cheng
2011-03-09	Fix typo, make helper static.	Benjamin Kramer
2011-03-08	Fix some latent bugs if the nodes are unschedulable. We'd gotten away	Eric Christopher
2011-03-08	Further improvements to pre-RA-sched=list-ilp.	Andrew Trick
2011-03-07	Move getRegPressureLimit() from TargetLoweringInfo to TargetRegisterInfo.	Cameron Zwarich
2011-03-06	Typo.	Eric Christopher
2011-03-06	Disable a couple of experimental heuristics to get the best results from the ...	Andrew Trick
2011-03-05	Be explicit with abs(). Visual Studio workaround.	Andrew Trick
2011-03-05	Missing comment.	Andrew Trick
2011-03-05	Increased the register pressure limit on x86_64 from 8 to 12	Andrew Trick
2011-03-04	Minor pre-RA-sched fixes and cleanup.	Andrew Trick
2011-02-04	Introducing a new method of tracking register pressure. We can't	Andrew Trick
2011-01-27	Remove a temporary workaround for a lencod miscompile. Depends on the fix in ...	Andrew Trick
2011-01-24	Temporarily workaround JM/lencod miscompile (SIGSEGV).	Andrew Trick
2011-01-21	Enable support for precise scheduling of the instruction selection	Andrew Trick
2011-01-21	Convert -enable-sched-cycles and -enable-sched-hazard to -disable	Andrew Trick
2011-01-20	Selection DAG scheduler register pressure heuristic fixes.	Andrew Trick
2011-01-14	Support for precise scheduling of the instruction selection DAG,	Andrew Trick
2010-12-24	Minor cleanup related to my latest scheduler changes.	Andrew Trick
2010-12-24	Fix a few cases where the scheduler is not checking for phys reg copies. The ...	Andrew Trick
2010-12-24	Various bits of framework needed for precise machine-level selection	Andrew Trick
2010-12-23	flags -> glue for selectiondag	Chris Lattner
2010-12-23	Reorganize ListScheduleBottomUp in preparation for modeling machine cycles an...	Andrew Trick
2010-12-23	Converted LiveRegCycles to LiveRegGens. It's easier to work with and allows m...	Andrew Trick
2010-12-23	In CheckForLiveRegDef use TRI->getOverlaps.	Andrew Trick
2010-12-23	Fixes PR8823: add-with-overflow-128.ll	Andrew Trick
2010-12-21	In DelayForLiveRegsBottomUp, handle instructions that read and write	Andrew Trick
2010-12-21	whitespace	Andrew Trick