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path: root/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
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2007-04-021. Insert custom lowering hooks for ISD::ROTR and ISD::ROTL.Scott Michel
2. Help DAGCombiner recognize zero/sign/any-extended versions of ROTR and ROTL patterns. This was motivated by the X86/rotate.ll testcase, which should now generate code for other platforms (and soon-to-come platforms.) Rewrote code slightly to make it easier to read. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35605 91177308-0d34-0410-b5e6-96231b3b80d8
2007-03-30Fix incorrect combination of different loads. Reenable zext-over-truncateDale Johannesen
combination. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35517 91177308-0d34-0410-b5e6-96231b3b80d8
2007-03-29Disable load width reduction xform of variant (zext (truncate load x)) forEvan Cheng
big endian targets until llvm-gcc build issue has been resolved. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35449 91177308-0d34-0410-b5e6-96231b3b80d8
2007-03-26SIGN_EXTEND_INREG requires one extra operand, a ValueType node.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35350 91177308-0d34-0410-b5e6-96231b3b80d8
2007-03-24Adjust offset to compensate for big endian machines.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35293 91177308-0d34-0410-b5e6-96231b3b80d8
2007-03-23Make sure SEXTLOAD of the specific type is supported on the target.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35289 91177308-0d34-0410-b5e6-96231b3b80d8
2007-03-23Also replace uses of SRL if that's also folded during ReduceLoadWidth().Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35286 91177308-0d34-0410-b5e6-96231b3b80d8
2007-03-23A couple of bug fixes for reducing load width xform:Evan Cheng
1. Address offset is in bytes. 2. Make sure truncate node uses are replaced with new load. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35274 91177308-0d34-0410-b5e6-96231b3b80d8
2007-03-22More opportunities to reduce load size.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35254 91177308-0d34-0410-b5e6-96231b3b80d8
2007-03-21fold (truncate (srl (load x), c)) -> (smaller load (x+c/vt bits))Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35239 91177308-0d34-0410-b5e6-96231b3b80d8
2007-03-07Avoid combining indexed load further.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35005 91177308-0d34-0410-b5e6-96231b3b80d8
2007-03-04fold away addc nodes when we know there cannot be a carry-out.Chris Lattner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34913 91177308-0d34-0410-b5e6-96231b3b80d8
2007-03-04generalizeChris Lattner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34910 91177308-0d34-0410-b5e6-96231b3b80d8
2007-03-04canonicalize constants to the RHS of addc/adde. If nothing uses the carry ↵Chris Lattner
out of addc, turn it into add. This allows us to compile: long long test(long long A, unsigned B) { return (A + ((long long)B << 32)) & 123; } into: _test: movl $123, %eax andl 4(%esp), %eax xorl %edx, %edx ret instead of: _test: xorl %edx, %edx movl %edx, %eax addl 4(%esp), %eax ;; add of zero andl $123, %eax ret git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34909 91177308-0d34-0410-b5e6-96231b3b80d8
2007-02-26Fold (sext (truncate x)) more aggressively, by avoiding creation of aChris Lattner
sextinreg if not needed. This is useful in two cases: before legalize, it avoids creating a sextinreg that will be trivially removed. After legalize if the target doesn't support sextinreg, the trunc/sext would not have been removed before. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34621 91177308-0d34-0410-b5e6-96231b3b80d8
2007-02-08Move SimplifySetCC to TargetLowering and allow it to be shared with legalizer.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34065 91177308-0d34-0410-b5e6-96231b3b80d8
2007-01-20Fix for PR1108: type of insert_vector_elt index operand is PtrVT, not MVT::i32.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33398 91177308-0d34-0410-b5e6-96231b3b80d8
2007-01-19Remove this xform:Evan Cheng
(shl (add x, c1), c2) -> (add (shl x, c2), c1<<c2) Replace it with: (add (shl (add x, c1), c2), ) -> (add (add (shl x, c2), c1<<c2), ) This fixes test/CodeGen/ARM/smul.ll git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33361 91177308-0d34-0410-b5e6-96231b3b80d8
2007-01-16Fix PR1114 and CodeGen/Generic/2007-01-15-LoadSelectCycle.ll by beingChris Lattner
careful when folding "c ? load p : load q" that C doesn't reach either load. If so, folding this into load (c ? p : q) will induce a cycle in the graph. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33251 91177308-0d34-0410-b5e6-96231b3b80d8
2007-01-16add options to view the dags before the first or second pass of dag combine.Chris Lattner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33249 91177308-0d34-0410-b5e6-96231b3b80d8
2007-01-08Implement some trivial FP foldings when -enable-unsafe-fp-math is specified.Chris Lattner
This implements CodeGen/PowerPC/unsafe-math.ll git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33024 91177308-0d34-0410-b5e6-96231b3b80d8
2006-12-19Eliminate static ctors from StatisticsChris Lattner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@32698 91177308-0d34-0410-b5e6-96231b3b80d8
2006-12-16Cannot combine an indexed load / store any further.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@32629 91177308-0d34-0410-b5e6-96231b3b80d8
2006-12-15This code was usurping the sextload expand in teh legalizer. Just makeJim Laskey
sure the right conditions are checked. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@32611 91177308-0d34-0410-b5e6-96231b3b80d8
2006-12-12make this code more aggressive about turning store fpimm into store int imm.Chris Lattner
This is not sufficient to fix X86/store-fp-constant.ll git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@32465 91177308-0d34-0410-b5e6-96231b3b80d8
2006-12-11Don't convert store double C, Ptr to store long C, Ptr if i64 is not a legal ↵Evan Cheng
type. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@32434 91177308-0d34-0410-b5e6-96231b3b80d8
2006-12-11Move something that should be in the dag combiner from the legalizer to theNate Begeman
dag combiner. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@32431 91177308-0d34-0410-b5e6-96231b3b80d8
2006-12-07Fix CodeGen/PowerPC/2006-12-07-SelectCrash.ll on PPC64Chris Lattner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@32336 91177308-0d34-0410-b5e6-96231b3b80d8
2006-12-07Removing even more <iostream> includes.Bill Wendling
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@32320 91177308-0d34-0410-b5e6-96231b3b80d8
2006-12-06Detemplatize the Statistic class. The only type it is instantiated withChris Lattner
is 'unsigned'. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@32279 91177308-0d34-0410-b5e6-96231b3b80d8
2006-11-27For better or worse, load from i1 is assumed to be zero extended. Do notChris Lattner
form a load from i1 from larger loads that may not be zext'd. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31933 91177308-0d34-0410-b5e6-96231b3b80d8
2006-11-20Fix PR1011 and CodeGen/Generic/2006-11-20-DAGCombineCrash.llChris Lattner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31878 91177308-0d34-0410-b5e6-96231b3b80d8
2006-11-16Fix an incorrectly inverted condition.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31773 91177308-0d34-0410-b5e6-96231b3b80d8
2006-11-11disallow preinc of a frameindex. This is not profitable and causes 2-addrChris Lattner
pass to explode. This fixes a bunch of llc-beta failures on ppc last night. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31661 91177308-0d34-0410-b5e6-96231b3b80d8
2006-11-11reduce indentation by using early exits. No functionality change.Chris Lattner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31660 91177308-0d34-0410-b5e6-96231b3b80d8
2006-11-11move big chunks of code out-of-line, no functionality change.Chris Lattner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31658 91177308-0d34-0410-b5e6-96231b3b80d8
2006-11-10Fix a dag combiner bug exposed by my recent instcombine patch. This fixesChris Lattner
CodeGen/Generic/2006-11-10-DAGCombineMiscompile.ll and PPC gsm/toast git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31644 91177308-0d34-0410-b5e6-96231b3b80d8
2006-11-10When forming a pre-indexed store, make sure ptr isn't the same or is a pred ↵Evan Cheng
of value being stored. It would cause a cycle. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31631 91177308-0d34-0410-b5e6-96231b3b80d8
2006-11-09Don't attempt expensive pre-/post- indexed dag combine if target does not ↵Evan Cheng
support them. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31598 91177308-0d34-0410-b5e6-96231b3b80d8
2006-11-09Rename ISD::MemOpAddrMode to ISD::MemIndexedModeEvan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31595 91177308-0d34-0410-b5e6-96231b3b80d8
2006-11-09getPostIndexedAddressParts change: passes in load/store instead of its ↵Evan Cheng
loaded / stored VT. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31584 91177308-0d34-0410-b5e6-96231b3b80d8
2006-11-08Match more post-indexed ops.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31569 91177308-0d34-0410-b5e6-96231b3b80d8
2006-11-08Remove redundant <cmath>.Jim Laskey
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31561 91177308-0d34-0410-b5e6-96231b3b80d8
2006-11-08- When performing pre-/post- indexed load/store transformation, do not worryEvan Cheng
about whether the new base ptr would be live below the load/store. Let two address pass split it back to non-indexed ops. - Minor tweaks / fixes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31544 91177308-0d34-0410-b5e6-96231b3b80d8
2006-11-08Fixed a minor bug preventing some pre-indexed load / store transformation.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31543 91177308-0d34-0410-b5e6-96231b3b80d8
2006-11-08Fix a obscure post-indexed load / store dag combine bug.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31537 91177308-0d34-0410-b5e6-96231b3b80d8
2006-11-07Add post-indexed load / store transformations.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31498 91177308-0d34-0410-b5e6-96231b3b80d8
2006-11-06Add comment.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31473 91177308-0d34-0410-b5e6-96231b3b80d8
2006-11-05Unbreak VC++ build.Jeff Cohen
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31464 91177308-0d34-0410-b5e6-96231b3b80d8
2006-11-05Added pre-indexed store support.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31459 91177308-0d34-0410-b5e6-96231b3b80d8
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