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2010-09-21simplify DAGCombiner::SimplifySelectOps step #2/2.Chris Lattner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114437 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-21substantially reduce indentation and simplify DAGCombiner::SimplifySelectOps.Chris Lattner
no functionality change (step #1) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114436 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-21a few more trivial updates. This fixes PerformInsertVectorEltInMemory to notChris Lattner
pass a completely incorrect SrcValue, which would result in a miscompile with combiner-aa. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114411 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-20When TCO is turned on, it is possible to end up with aliasing FrameIndex's. ↵Owen Anderson
Therefore, CombinerAA cannot assume that different FrameIndex's never alias, but can instead use MachineFrameInfo to get the actual offsets of these slots and check for actual aliasing. This fixes CodeGen/X86/2010-02-19-TailCallRetAddrBug.ll and CodeGen/X86/tailcallstack64.ll when CombinerAA is enabled, modulo a different register allocation sequence. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114348 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-19Revert r114312 while I sort out some issues.Owen Anderson
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114313 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-19Tentatively enabled DAGCombiner Alias Analysis by default. As far as I know,Owen Anderson
r114268 fixed the last of the blockers to enabling it. I will be monitoring for failures. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114312 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-02Don't narrow the load and store in a load+twiddle+store sequence unlessDan Gohman
there are clearly no stores between the load and the store. This fixes this miscompile reported as PR7833. This breaks the test/CodeGen/X86/narrow_op-2.ll optimization, which is safe, but awkward to prove safe. Move it to X86's README.txt. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112861 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-27Fix a crash in the dag combiner caused by ↵Nate Begeman
ConstantFoldBIT_CONVERTofBUILD_VECTOR calling itself recursively and returning a SCALAR_TO_VECTOR node, but assuming the input was always a BUILD_VECTOR. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109519 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-19Remove r108639 now that it is handled by InstCombine instead.Owen Anderson
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108688 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-18Add a DAGCombine xform to fold away redundant float->double->float ↵Owen Anderson
conversions around sqrt instructions. I am assured by people more knowledgeable than me that there are no rounding issues in eliminating this. This fixed <rdar://problem/8197504>. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108639 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-12Convert some tab stops into spaces.Duncan Sands
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108130 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-09Reenable DAG combining for vector shuffles. It looks like it was temporarilyBob Wilson
disabled and then never turned back on again. Adjust some tests, one because this change avoids an unnecessary instruction, and the other to make it continue testing what it was intended to test. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107941 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-08Merge the duplicated iabs optimization in DAGCombiner and let it detected a ↵Benjamin Kramer
few more idioms. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107868 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-07Move getExtLoad() and (some) getLoad() DebugLoc argument after EVT argument ↵Evan Cheng
for consistency sake. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107820 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-06Propagate debug loc.Devang Patel
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107710 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-28Unlike other targets, ARM now uses BUILD_VECTORs post-legalization so theyBob Wilson
can't be changed arbitrarily by the DAGCombiner without checking if it is running after legalization. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107097 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-25Remove variables which are assigned to but for which the valueDuncan Sands
is not used. Spotted by gcc-4.6. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106854 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-24Reapply r106634, now that the bug it exposed is fixed.Dan Gohman
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106746 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-23Revert r106263, "Fold the ShrinkDemandedOps pass into the regular ↵Daniel Dunbar
DAGCombiner pass,"... it was causing both 'file' (with clang) and 176.gcc (with llvm-gcc) to be miscompiled. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106634 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-23Some targets don't require the fencing MEMBARRIER instructions surroundingJim Grosbach
atomic intrinsics, either because the use locking instructions for the atomics, or because they perform the locking directly. Add support in the DAG combiner to fold away the fences. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106630 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-18Fold the ShrinkDemandedOps pass into the regular DAGCombiner pass,Dan Gohman
which is faster, simpler, and less surprising. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106263 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-25Fix another variant of PR 7191. Also add a testcaseDale Johannesen
Mon Ping provided; unfortunately bugpoint failed to reduce it, but I think it's important to have a test for this in the suite. 8023512. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104624 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-25Fix PR 7191. I have been unable to create a .ll file that fails, sorry.Dale Johannesen
(oye, a word which should be better known to people writing tree traversals, means grandchild.) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104619 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-21Clean up extra whitespace.Bob Wilson
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104410 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-21Change CodeGen/ARM/2009-11-02-NegativeLane.ll to use 16-bit vector elementsBob Wilson
so that it will continue to test what it was meant to test when I commit a separate change for better support of BUILD_VECTOR and VECTOR_SHUFFLE for Neon. Fix a DAG combiner crash exposed by this test change. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104380 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-19Optimize away insertelement of an undef value. This shows up inBob Wilson
test/Codegen/ARM/reg_sequence.ll but it doesn't affect the generated code because the coalescer cleans it up. Radar 7998853. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104185 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-19Intrinsics which do a vector compare (results are all zero or all ones) are ↵Evan Cheng
modeled as icmp / fcmp + sext. This is turned into a vsetcc by dag combine (yes, not a good long term solution). The targets can then isel the vsetcc to the appropriate instruction. The trouble arises when the result of a vector cmp + sext is then and'ed with all ones. Instcombine will turn it into a vector cmp + zext, dag combiner will miss turning it into a vsetcc and hell breaks loose after that. Teach dag combine to turn a vector cpm + zest into a vsetcc + and 1. This fixes rdar://7923010. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104094 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-18Sink dag combine's post index load / store code that swap base ptr and index ↵Evan Cheng
into the target hook. Only the target knows whether the swap is safe. In Thumb2 mode, the offset must be an immediate. rdar://7998649 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104060 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-18FIX PR7158. SimplifyVBinOp was asserting when it fails to constant fold (op ↵Evan Cheng
(build_vector), (build_vector)). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104004 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-10Be careful with operand promotion. For a binary operation, the source ↵Evan Cheng
operands may be the same. PR7018. rdar://7939869. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103419 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-30Apply a patch from Jan Sjodin to fix a compiler abort on vectorDan Gohman
comparisons sign-extended to a different bitwidth than the comparison operands. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102721 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-28Try operation promotion only if regular dag combine and target-specific ones ↵Evan Cheng
failed to do anything. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102492 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-27- When legal, promote a load to zextload rather than ext load.Evan Cheng
- Catch more further dag combine opportunities as result of operand promotion, e.g. (i32 anyext (i16 trunc (i32 x))) -> (i32 x) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102455 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-24When a load operand is promoted to an extload, replace other uses with uses ↵Evan Cheng
of extload result truncated. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102236 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-24Apply a fix for a vector setcc dagcombine from Jan Sjodin. NoDan Gohman
testcase yet, as the testcase now fails downstream. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102228 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-23Code refactoring.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102202 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-22- It's not safe to promote rotates (at least not trivially).Evan Cheng
- Some code refactoring. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102111 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-20The visitXOR method can return the same SDNode. If so, we don't want to deleteBill Wendling
it as it's not dead. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101855 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-19More progress on promoting i16 operations to i32 for x86. Work in progress.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101808 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-17More work to allow dag combiner to promote 16-bit ops to 32-bit.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101621 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-16(i32 sext_in_reg (i32 aext (i16 x)), i16) -> (i32 sext x). No known test ↵Evan Cheng
case until -promote-16bit is enabled. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101551 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-16Adding support for dag combiner to promote operations for profit. This ↵Evan Cheng
requires target specific queries. For example, x86 should promote i16 to i32 when it does not impact load folding. x86 support is off by default. It can be enabled with -promote-16bit. Work in progress. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101448 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-15enhance the load/store narrowing optimization to handle aChris Lattner
tokenfactor in between the load/store. This allows us to optimize test7 into: _test7: ## @test7 ## BB#0: ## %entry movl (%rdx), %eax ## kill: SIL<def> ESI<kill> movb %sil, 5(%rdi) ret instead of: _test7: ## @test7 ## BB#0: ## %entry movl 4(%esp), %ecx movl $-65281, %eax ## imm = 0xFFFFFFFFFFFF00FF andl 4(%ecx), %eax movzbl 8(%esp), %edx shll $8, %edx addl %eax, %edx movl 12(%esp), %eax movl (%eax), %eax movl %edx, 4(%ecx) ret git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101355 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-15teach codegen to turn trunc(zextload) into load when possible.Chris Lattner
This doesn't occur much at all, it only seems to formed in the case when the trunc optimization kicks in due to phase ordering. In that case it is saves a few bytes on x86-32. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101350 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-15add a simple dag combine to replace trivial shl+lshr withChris Lattner
and. This happens with the store->load narrowing stuff. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101348 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-15Implement rdar://7860110 (also in target/readme.txt) narrowingChris Lattner
a load/or/and/store sequence into a narrower store when it is safe. Daniel tells me that clang will start producing this sort of thing with bitfields, and this does trigger a few dozen times on 176.gcc produced by llvm-gcc even now. This compiles code like CodeGen/X86/2009-05-28-DAGCombineCrash.ll into: movl %eax, 36(%rdi) instead of: movl $4294967295, %eax ## imm = 0xFFFFFFFF andq 32(%rdi), %rax shlq $32, %rcx addq %rax, %rcx movq %rcx, 32(%rdi) and each of the testcases into a single store. Each of them used to compile into craziness like this: _test4: movl $65535, %eax ## imm = 0xFFFF andl (%rdi), %eax shll $16, %esi addl %eax, %esi movl %esi, (%rdi) ret git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101343 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-15Add const qualifiers to CodeGen's use of LLVM IR constructs.Dan Gohman
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101334 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-12Remove unnecessary parens.Dan Gohman
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101010 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-08Fix -Wsign-compare warning (issued by clang++).Ted Kremenek
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100799 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-07fix 80 col violation, patch by Alastair LynnChris Lattner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100639 91177308-0d34-0410-b5e6-96231b3b80d8
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