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path: root/lib/CodeGen/ScheduleDAGInstrs.cpp
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2011-04-15Fix a ton of comment typos found by codespell. Patch byChris Lattner
Luis Felipe Strano Moraes! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129558 91177308-0d34-0410-b5e6-96231b3b80d8
2011-01-07Do not model all INLINEASM instructions as having unmodelled side effects.Evan Cheng
Instead encode llvm IR level property "HasSideEffects" in an operand (shared with IsAlignStack). Added MachineInstrs::hasUnmodeledSideEffects() to check the operand when the instruction is an INLINEASM. This allows memory instructions to be moved around INLINEASM instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123044 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-15Move Value::getUnderlyingObject to be a standaloneDan Gohman
function so that it can live in Analysis instead of VMCore. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121885 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-03Two sets of changes. Sorry they are intermingled.Evan Cheng
1. Fix pre-ra scheduler so it doesn't try to push instructions above calls to "optimize for latency". Call instructions don't have the right latency and this is more likely to use introduce spills. 2. Fix if-converter cost function. For ARM, it should use instruction latencies, not # of micro-ops since multi-latency instructions is completely executed even when the predicate is false. Also, some instruction will be "slower" when they are predicated due to the register def becoming implicit input. rdar://8598427 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118135 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-27Putting r117193 back except for the compile time cost. Rather than assuming ↵Evan Cheng
fallthroughs uses all registers, just gather the union of all successor liveins. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117506 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-25Neuter r117193 as it causes significant post-ra scheduler compile time ↵Evan Cheng
regression. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117329 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-23Properly model the latency of register defs which are 1) function returns orEvan Cheng
2) live-outs. Previously the post-RA schedulers completely ignore these dependencies since returns, branches, etc. are all scheduling barriers. This patch model the latencies between instructions being scheduled and the barriers. It also handle calls by marking their register uses. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117193 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-08Avoid compiler warning: comparison between signed and unsigned integer.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116119 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-08Fix operand latency computation in cases where the definition operand isEvan Cheng
implicit. e.g. %D6<def>, %D7<def> = VLD1q16 %R2<kill>, 0, ..., %Q3<imp-def> %Q1<def> = VMULv8i16 %Q1<kill>, %Q3<kill>, ... The real definition indices are 0,1. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116080 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-06Remove unused variables.Nick Lewycky
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115802 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-06- Add TargetInstrInfo::getOperandLatency() to compute operand latencies. ThisEvan Cheng
allow target to correctly compute latency for cases where static scheduling itineraries isn't sufficient. e.g. variable_ops instructions such as ARM::ldm. This also allows target without scheduling itineraries to compute operand latencies. e.g. X86 can return (approximated) latencies for high latency instructions such as division. - Compute operand latencies for those defined by load multiple instructions, e.g. ldm and those used by store multiple instructions, e.g. stm. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115755 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-29Model Cortex-a9 load to SUB, RSB, ADD, ADC, SBC, RSC, CMN, MVN, or CMPEvan Cheng
pipeline forwarding path. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115098 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-10Teach if-converter to be more careful with predicating instructions that wouldEvan Cheng
take multiple cycles to decode. For the current if-converter clients (actually only ARM), the instructions that are predicated on false are not nops. They would still take machine cycles to decode. Micro-coded instructions such as LDM / STM can potentially take multiple cycles to decode. If-converter should take treat them as non-micro-coded simple instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113570 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-24Change ScheduleDAGInstrs::Defs and ::Uses to be variable-size vectorsBob Wilson
instead of fixed size arrays, so that increasing FirstVirtualRegister to 16K won't cause a compile time performance regression. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109330 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-15Use std::vector instead of TargetRegisterInfo::FirstVirtualRegister.Bill Wendling
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108452 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-19Fix the post-RA instruction scheduler to handle instructions referenced byJim Grosbach
more than one dbg_value instruction. rdar://7759363 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104174 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-01Get rid of the EdgeMapping map. Instead, just check for BasicBlockDan Gohman
changes before doing phi lowering for switches. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102809 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-17Fix -Wcast-qual warnings.Dan Gohman
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101655 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-22Reduce indentation.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99214 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-2280 col violation.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99195 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-10Progress towards shepherding debug info through SelectionDAG.Dale Johannesen
No functional effect yet. This is still evolving and should not be viewed as final. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98195 91177308-0d34-0410-b5e6-96231b3b80d8
2010-02-16There are two ways of checking for a given type, for example isa<PointerType>(T)Duncan Sands
and T->isPointerTy(). Convert most instances of the first form to the second form. Requested by Chris. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96344 91177308-0d34-0410-b5e6-96231b3b80d8
2009-11-09Fix dependencies added to model memory aliasing for post-RA scheduling. The ↵David Goodwin
dependencies were overly conservative for memory access that are known not to alias. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86580 91177308-0d34-0410-b5e6-96231b3b80d8
2009-11-05Correctly add chain dependencies around calls and unknown-side-effect ↵David Goodwin
instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86080 91177308-0d34-0410-b5e6-96231b3b80d8
2009-11-03<rdar://problem/7352605>. When building schedule graph use mayAlias ↵David Goodwin
information to avoid chaining loads/stores of spill slots with non-aliased memory ops. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85934 91177308-0d34-0410-b5e6-96231b3b80d8
2009-11-02Chain dependencies used to enforce memory order should have latency of 0 ↵David Goodwin
(except for true dependency of Store followed by aliased Load... we estimate that case with a single cycle of latency assuming the hardware will bypass) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85807 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-26When checking whether a def of an aliased register is dead, ask theDan Gohman
machineinstr whether the aliased register is dead, rather than the original register is dead. This allows it to get the correct answer when examining an instruction like this: CALLpcrel32 <ga:foo>, %AL<imp-def>, %EAX<imp-def,dead> where EAX is dead but a subregister of it is still live. This fixes PR5294. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85135 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-18Spill slots cannot alias.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84432 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-18-Revert parts of 84326 and 84411. Distinquishing between fixed and non-fixedEvan Cheng
stack slots and giving them different PseudoSourceValue's did not fix the problem of post-alloc scheduling miscompiling llvm itself. - Apply Dan's conservative workaround by assuming any non fixed stack slots can alias other memory locations. This means a load from spill slot #1 cannot move above a store of spill slot #2. - Enable post-alloc scheduling for x86 at optimization leverl Default and above. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84424 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-09Factor out LiveIntervalAnalysis' code to determine whether an instructionDan Gohman
is trivially rematerializable and integrate it into TargetInstrInfo::isTriviallyReMaterializable. This way, all places that need to know whether an instruction is rematerializable will get the same answer. This enables the useful parts of the aggressive-remat option by default -- using AliasAnalysis to determine whether a memory location is invariant, and removes the questionable parts -- rematting operations with virtual register inputs that may not be live everywhere. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83687 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-07Replace TargetInstrInfo::isInvariantLoad and its target-specificDan Gohman
implementations with a new MachineInstr::isInvariantLoad, which uses MachineMemOperands and is target-independent. This brings MachineLICM and other functionality to targets which previously lacked an isInvariantLoad implementation. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83475 91177308-0d34-0410-b5e6-96231b3b80d8
2009-09-25Improve MachineMemOperand handling.Dan Gohman
- Allocate MachineMemOperands and MachineMemOperand lists in MachineFunctions. This eliminates MachineInstr's std::list member and allows the data to be created by isel and live for the remainder of codegen, avoiding a lot of copying and unnecessary translation. This also shrinks MemSDNode. - Delete MemOperandSDNode. Introduce MachineSDNode which has dedicated fields for MachineMemOperands. - Change MemSDNode to have a MachineMemOperand member instead of its own fields with the same information. This introduces some redundancy, but it's more consistent with what MachineInstr will eventually want. - Ignore alignment when searching for redundant loads for CSE, but remember the greatest alignment. Target-specific code which previously used MemOperandSDNodes with generic SDNodes now use MemIntrinsicSDNodes, with opcodes in a designated range so that the SelectionDAG framework knows that MachineMemOperand information is available. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82794 91177308-0d34-0410-b5e6-96231b3b80d8
2009-09-18Enhance EmitInstrWithCustomInserter() so target can specify CFG changes that ↵Evan Cheng
sdisel will use to properly complete phi nodes. Not functionality change yet. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82273 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-19Use the schedule itinerary operand use/def cycle information to adjust ↵David Goodwin
dependence edge latency for post-RA scheduling. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79425 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-13Add callback to allow target to adjust latency of schedule dependency edge.David Goodwin
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78910 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-10Post RA scheduler changes. Introduce a hazard recognizer that uses the ↵David Goodwin
target schedule information to accurately model the pipeline. Update the scheduler to correctly handle multi-issue targets. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78563 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-07Fix a typo in a comment.Dan Gohman
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78362 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-17Eliminate yet another copy of getOpcode.Dan Gohman
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76236 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-13Move isLCSSAForm, isLoopInvariant, getCanonicalInductionVariable,Dan Gohman
and related functions out of LoopBase and into Loop, since they are specific to BasicBlock-based loops. This also allows the code to be moved out-of-line. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75523 91177308-0d34-0410-b5e6-96231b3b80d8
2009-02-11When scheduling a block in parts, keep track of the overallDan Gohman
instruction index across each part. Instruction indices are used to make live range queries, and live ranges can extend beyond scheduling region boundaries. Refactor the ScheduleDAGSDNodes class some more so that it doesn't have to worry about this additional information. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@64288 91177308-0d34-0410-b5e6-96231b3b80d8
2009-02-10Factor out more code for computing register live-range informationforDan Gohman
scheduling, and generalize is so that preserves state across scheduling regions. This fixes incorrect live-range information around terminators and labels, which are effective region boundaries. In place of looking for terminators to anchor inter-block dependencies, introduce special entry and exit scheduling units for this purpose. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@64254 91177308-0d34-0410-b5e6-96231b3b80d8
2009-02-06Move ScheduleDAGInstrs.h to be a private header. Front-endsDan Gohman
that used this header to select a scheduling policy should use SchedulerRegistry.h instead (llvm-gcc and clang were updated a while ago). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63934 91177308-0d34-0410-b5e6-96231b3b80d8
2009-01-30Fix a post-RA scheduling dependency bug.Dan Gohman
If a MachineInstr doesn't have a memoperand but has an opcode that is known to load or store, assume its memory reference may alias *anything*, including stack slots which the compiler completely controls. To partially compensate for this, teach the ScheduleDAG building code to do basic getUnderlyingValue analysis. This greatly reduces the number of instructions that require restrictive dependencies. This code will need to be revisited when we start doing real alias analysis, but it should suffice for now. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63370 91177308-0d34-0410-b5e6-96231b3b80d8
2009-01-16Instead of adding dependence edges between terminator instructionsDan Gohman
and every other instruction in their blocks to keep the terminator instructions at the end, teach the post-RA scheduler how to operate on ranges of instructions, and exclude terminators from the range of instructions that get scheduled. Also, exclude mid-block labels, such as EH_LABEL instructions, and schedule code before them separately from code after them. This fixes problems with the post-RA scheduler moving code past EH_LABELs. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62366 91177308-0d34-0410-b5e6-96231b3b80d8
2009-01-15Move a few containers out of ScheduleDAGInstrs::BuildSchedGraphDan Gohman
and into the ScheduleDAGInstrs class, so that they don't get destructed and re-constructed for each block. This fixes a compile-time hot spot in the post-pass scheduler. To help facilitate this, tidy and do some minor reorganization in the scheduler constructor functions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62275 91177308-0d34-0410-b5e6-96231b3b80d8
2008-12-23Clean up the atomic opcodes in SelectionDAG.Dan Gohman
This removes all the _8, _16, _32, and _64 opcodes and replaces each group with an unsuffixed opcode. The MemoryVT field of the AtomicSDNode is now used to carry the size information. In tablegen, the size-specific opcodes are replaced by size-independent opcodes that utilize the ability to compose them with predicates. This shrinks the per-opcode tables and makes the code that handles atomics much more concise. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@61389 91177308-0d34-0410-b5e6-96231b3b80d8
2008-12-23Rename BuildSchedUnits to BuildSchedGraph, and refactor theDan Gohman
code in ScheduleDAGSDNodes' BuildSchedGraph into separate functions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@61376 91177308-0d34-0410-b5e6-96231b3b80d8
2008-12-23Use isTerminator() instead of isBranch()||isReturn() inDan Gohman
several places. isTerminator() returns true for a superset of cases, and includes things like FP_REG_KILL, which are nither return or branch but aren't safe to move/remat/etc. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@61373 91177308-0d34-0410-b5e6-96231b3b80d8
2008-12-16Add initial support for back-scheduling address computations,Dan Gohman
especially in the case of addresses computed from loop induction variables. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@61075 91177308-0d34-0410-b5e6-96231b3b80d8
2008-12-16Fix some register-alias-related bugs in the post-RA scheduler livenessDan Gohman
computation code. Also, avoid adding output-depenency edges when both defs are dead, which frequently happens with EFLAGS defs. Compute Depth and Height lazily, and always in terms of edge latency values. For the schedulers that don't care about latency, edge latencies are set to 1. Eliminate Cycle and CycleBound, and LatencyPriorityQueue's Latencies array. These are all subsumed by the Depth and Height fields. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@61073 91177308-0d34-0410-b5e6-96231b3b80d8
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