| Age | Commit message (Expand) | Author |
|---|
| 2010-05-19 | Fix the post-RA instruction scheduler to handle instructions referenced by | Jim Grosbach |
| 2010-05-01 | Get rid of the EdgeMapping map. Instead, just check for BasicBlock | Dan Gohman |
| 2010-04-17 | Fix -Wcast-qual warnings. | Dan Gohman |
| 2010-03-22 | Reduce indentation. | Evan Cheng |
| 2010-03-22 | 80 col violation. | Evan Cheng |
| 2010-03-10 | Progress towards shepherding debug info through SelectionDAG. | Dale Johannesen |
| 2010-02-16 | There are two ways of checking for a given type, for example isa<PointerType>(T) | Duncan Sands |
| 2009-11-09 | Fix dependencies added to model memory aliasing for post-RA scheduling. The d... | David Goodwin |
| 2009-11-05 | Correctly add chain dependencies around calls and unknown-side-effect instruc... | David Goodwin |
| 2009-11-03 | <rdar://problem/7352605>. When building schedule graph use mayAlias informati... | David Goodwin |
| 2009-11-02 | Chain dependencies used to enforce memory order should have latency of 0 (exc... | David Goodwin |
| 2009-10-26 | When checking whether a def of an aliased register is dead, ask the | Dan Gohman |
| 2009-10-18 | Spill slots cannot alias. | Evan Cheng |
| 2009-10-18 | -Revert parts of 84326 and 84411. Distinquishing between fixed and non-fixed | Evan Cheng |
| 2009-10-09 | Factor out LiveIntervalAnalysis' code to determine whether an instruction | Dan Gohman |
| 2009-10-07 | Replace TargetInstrInfo::isInvariantLoad and its target-specific | Dan Gohman |
| 2009-09-25 | Improve MachineMemOperand handling. | Dan Gohman |
| 2009-09-18 | Enhance EmitInstrWithCustomInserter() so target can specify CFG changes that ... | Evan Cheng |
| 2009-08-19 | Use the schedule itinerary operand use/def cycle information to adjust depend... | David Goodwin |
| 2009-08-13 | Add callback to allow target to adjust latency of schedule dependency edge. | David Goodwin |
| 2009-08-10 | Post RA scheduler changes. Introduce a hazard recognizer that uses the target... | David Goodwin |
| 2009-08-07 | Fix a typo in a comment. | Dan Gohman |
| 2009-07-17 | Eliminate yet another copy of getOpcode. | Dan Gohman |
| 2009-07-13 | Move isLCSSAForm, isLoopInvariant, getCanonicalInductionVariable, | Dan Gohman |
| 2009-02-11 | When scheduling a block in parts, keep track of the overall | Dan Gohman |
| 2009-02-10 | Factor out more code for computing register live-range informationfor | Dan Gohman |
| 2009-02-06 | Move ScheduleDAGInstrs.h to be a private header. Front-ends | Dan Gohman |
| 2009-01-30 | Fix a post-RA scheduling dependency bug. | Dan Gohman |
| 2009-01-16 | Instead of adding dependence edges between terminator instructions | Dan Gohman |
| 2009-01-15 | Move a few containers out of ScheduleDAGInstrs::BuildSchedGraph | Dan Gohman |
| 2008-12-23 | Clean up the atomic opcodes in SelectionDAG. | Dan Gohman |
| 2008-12-23 | Rename BuildSchedUnits to BuildSchedGraph, and refactor the | Dan Gohman |
| 2008-12-23 | Use isTerminator() instead of isBranch()||isReturn() in | Dan Gohman |
| 2008-12-16 | Add initial support for back-scheduling address computations, | Dan Gohman |
| 2008-12-16 | Fix some register-alias-related bugs in the post-RA scheduler liveness | Dan Gohman |
| 2008-12-16 | Add a simple target-independent heuristic to allow targets with no | Dan Gohman |
| 2008-12-09 | Rewrite the SDep class, and simplify some of the related code. | Dan Gohman |
| 2008-12-08 | Fix the top-level comments, and fix some 80-column violations. | Dan Gohman |
| 2008-12-04 | Add minimal support for disambiguating memory references. Currently | Dan Gohman |
| 2008-11-24 | Pass the isAntiDep argument. | Dan Gohman |
| 2008-11-21 | Correctly set the isCtrl flag for chain dependencies. | Dan Gohman |
| 2008-11-21 | Update comments. | Dan Gohman |
| 2008-11-21 | Set the isAntiDep flag in the MachineInstr scheduler. | Dan Gohman |
| 2008-11-21 | Use ComputeLatency in the MachineInstr scheduler. | Dan Gohman |
| 2008-11-21 | Implement ComputeLatency for MachineInstr ScheduleDAGs. Factor | Dan Gohman |
| 2008-11-20 | Treat mid-block labels the same as terminators when building the | Dan Gohman |
| 2008-11-19 | Experimental post-pass scheduling support. Post-pass scheduling | Dan Gohman |
