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Age	Commit message (Expand)	Author
2012-04-13	misched: Added CanHandleTerminators.	Andrew Trick
2012-03-16	ScheduleDAGInstrs: When adding uses we add them into a set that's empty at th...	Benjamin Kramer
2012-03-16	misched: add DAG edges from vreg defs to ExitSU.	Andrew Trick
2012-03-14	misched: implemented a framework for top-down or bottom-up scheduling.	Andrew Trick
2012-03-09	misched interface: rename Begin/End to RegionBegin/RegionEnd since they are n...	Andrew Trick
2012-03-07	misched prep: Expose the ScheduleDAGInstrs interface so targets may	Andrew Trick
2012-03-07	misched prep: Comment the ScheduleDAGInstrs interface.	Andrew Trick
2012-03-07	misched prep: Cleanup ScheduleDAGInstrs interface.	Andrew Trick
2012-03-07	misched prep: rename InsertPos to End.	Andrew Trick
2012-03-07	misched preparation: rename core scheduler methods for consistency.	Andrew Trick
2012-03-07	misched preparation: clarify ScheduleDAG and ScheduleDAGInstrs roles.	Andrew Trick
2012-03-07	misched preparation: modularize schedule emission.	Andrew Trick
2012-03-07	Cleanup in preparation for misched: Move DAG visualization logic.	Andrew Trick
2012-03-04	Use uint16_t to store register overlaps to reduce static data.	Craig Topper
2012-02-24	PostRA sched: speed up physreg tracking by not abusing SparseSet.	Andrew Trick
2012-02-23	misched: cleanup reaching def computation	Andrew Trick
2012-02-23	PostRASched: Convert physreg def/use tracking to Jakob's SparseSet.	Andrew Trick
2012-02-22	Don't compute latencies for regmask operands.	Jakob Stoklund Olesen
2012-02-22	misched: Use SparseSet for VRegDegs for constant time clear().	Andrew Trick
2012-02-22	Comment from code review	Andrew Trick
2012-02-22	misched: DAG builder should not track dependencies for SSA defs.	Andrew Trick
2012-02-22	Initialize SUnits before DAG building.	Andrew Trick
2012-02-21	Clear virtual registers after they are no longer referenced.	Andrew Trick
2012-01-14	misched: Initial code for building an MI level scheduling DAG	Andrew Trick
2012-01-14	Move physreg dependency generation into aptly named addPhysRegDeps.	Andrew Trick
2012-01-14	misched: Added ScheduleDAGInstrs::IsPostRA	Andrew Trick
2012-01-07	Added a late machine instruction copy propagation pass. This catches	Evan Cheng
2012-01-05	Remove an unused variable.	Chandler Carruth
2012-01-05	Minor postra scheduler cleanup. It could result in more precise antidependenc...	Andrew Trick
2011-12-14	Model ARM predicated write as read-mod-write. e.g.	Evan Cheng
2011-12-14	Allow target to specify register output dependency. Still default to one.	Evan Cheng
2011-12-14	- Add MachineInstrBundle.h and MachineInstrBundle.cpp. This includes a function	Evan Cheng
2011-12-07	Add bundle aware API for querying instruction properties and switch the code	Evan Cheng
2011-12-06	First chunk of MachineInstr bundle support.	Evan Cheng
2011-12-02	make sure ScheduleDAGInstrs::EmitSchedule does not crash when the first instr...	Hal Finkel
2011-10-07	PostRA scheduler fix. Clear stale loop dependencies.	Andrew Trick
2011-10-07	whitespace	Andrew Trick
2011-07-01	Rename TargetSubtarget to TargetSubtargetInfo for consistency.	Evan Cheng
2011-06-29	Sink SubtargetFeature and TargetInstrItineraries (renamed MCInstrItineraries)...	Evan Cheng
2011-06-28	- Rename TargetInstrDesc, TargetOperandInfo to MCInstrDesc and MCOperandInfo and	Evan Cheng
2011-06-02	Remove dead code.	Devang Patel
2011-06-02	Update DBG_VALUEs while breaking anti dependencies.	Devang Patel
2011-06-02	During post RA scheduling, do not try to chase reg defs. to preserve DBG_VALU...	Devang Patel
2011-05-06	Added an assertion, and updated a comment.	Andrew Trick
2011-05-05	ARM post RA scheduler compile time fix.	Andrew Trick
2011-05-05	whitespace	Andrew Trick
2011-04-15	Fix a ton of comment typos found by codespell. Patch by	Chris Lattner
2011-01-07	Do not model all INLINEASM instructions as having unmodelled side effects.	Evan Cheng
2010-12-15	Move Value::getUnderlyingObject to be a standalone	Dan Gohman
2010-11-03	Two sets of changes. Sorry they are intermingled.	Evan Cheng