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consistent with the other two
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@11723 91177308-0d34-0410-b5e6-96231b3b80d8
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allocators as well
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@11720 91177308-0d34-0410-b5e6-96231b3b80d8
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parts of the compiler
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@11655 91177308-0d34-0410-b5e6-96231b3b80d8
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1. LiveIntervals now implement a 4 slot per instruction model. Load,
Use, Def and a Store slot. This is required in order to correctly
represent caller saved register clobbering on function calls,
register reuse in the same instruction (def resues last use) and
also spill code added later by the allocator. The previous
representation (2 slots per instruction) was insufficient and as a
result was causing subtle bugs.
2. Fixes in spill code generation. This was the major cause of
failures in the test suite.
3. Linear scan now has core support for folding memory operands. This
is untested and not enabled (the live interval update function does
not attempt to fold loads/stores in instructions).
4. Lots of improvements in the debugging output of both live intervals
and linear scan. Give it a try... it is beautiful :-)
In summary the above fixes all the issues with the recent reserved
register elimination changes and get the allocator very close to the
next big step: folding memory operands.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@11619 91177308-0d34-0410-b5e6-96231b3b80d8
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std::numeric_limits<float>::max() for weighting preallocated
intervals.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@11393 91177308-0d34-0410-b5e6-96231b3b80d8
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ilist of MachineInstr objects. This allows constant time removal and
insertion of MachineInstr instances from anywhere in each
MachineBasicBlock. It also allows for constant time splicing of
MachineInstrs into or out of MachineBasicBlocks.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@11151 91177308-0d34-0410-b5e6-96231b3b80d8
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of the virtual register to certain functions.
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operand of the instruction and thus simplify the register allocation.
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spilled, A was loaded from its stack location twice. This fixes the bug.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@11088 91177308-0d34-0410-b5e6-96231b3b80d8
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much better when I get rid of the reserved registers.
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registers (not as the max number of registers).
Change toSpill from a std::set into a std::vector<bool>.
Use the reverse iterator adapter to do a reverse scan of allocatable
registers.
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where appropriate.
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MRegisterInfo::isVirtualRegister.
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is a move between two registers, at least one of the registers is
virtual and the two live intervals do not overlap.
This results in about 40% reduction in intervals, 30% decrease in the
register allocators running time and a 20% increase in peephole
optimizations (mainly move eliminations).
The option can be enabled by passing -join-liveintervals where
appropriate.
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with the current one.
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virtReg lives on the stack. Now a virtual register has an entry in the
virtual->physical map or the virtual->stack slot map but never in
both.
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register yet (2nd try).
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register yet.
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LiveIntervals::Interval::expiredAt() and simplify regalloc code.
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overlap before adding their spill weight.
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of the register allocator as follows:
before after
mesa 2.3790 1.5994
vpr 2.6008 1.2078
gcc 1.9840 0.5273
mcf 0.2569 0.0470
eon 1.8468 1.4359
twolf 0.9475 0.2004
burg 1.6807 1.3300
lambda 1.2191 0.3764
Speedups range anyware from 30% to over 400% :-)
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saved register it has a longer free range than ECX (which is defined
every time there is a fnuction call) which makes ECX a better register
to reserve.
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which denotes the register we would like to be assigned to (virtual or
physical). In register allocation, if this hint exists and we can map
it to a physical register (it is either a physical register or it is a
virtual register that already got assigned to a physical one) we use
that register if it is available instead of a random one in the free
pool.
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allocation in the presence of preallocated intervals.
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nesting level when computing it. Right now the allocator uses:
w = sum_over_defs_uses( 10 ^ nesting level );
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@10569 91177308-0d34-0410-b5e6-96231b3b80d8
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for live ranges that fall into assigned registers' holes.
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Add a statistic for # reloads
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instruction pass. This also fixes all remaining bugs for this new
allocator to pass all tests under test/Programs.
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are not reserved registers.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@10511 91177308-0d34-0410-b5e6-96231b3b80d8
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a) remove opIsUse(), opIsDefOnly(), opIsDefAndUse()
b) add isUse(), isDef()
c) rename opHiBits32() to isHiBits32(),
opLoBits32() to isLoBits32(),
opHiBits64() to isHiBits64(),
opLoBits64() to isLoBits64().
This results to much more readable code, for example compare
"op.opIsDef() || op.opIsDefAndUse()" to "op.isDef()" a pattern used
very often in the code.
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register too.
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