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path: root/lib/CodeGen/LowerSubregs.cpp
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2008-06-16Do not issue identity copies.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@52373 91177308-0d34-0410-b5e6-96231b3b80d8
2008-06-04Revert this.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@51949 91177308-0d34-0410-b5e6-96231b3b80d8
2008-06-04LowerSubregs should not clobber any analysis.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@51933 91177308-0d34-0410-b5e6-96231b3b80d8
2008-03-16Make insert_subreg a two-address instruction, vastly simplifying ↵Christopher Lamb
LowerSubregs pass. Add a new TII, subreg_to_reg, which is like insert_subreg except that it takes an immediate implicit value to insert into rather than a register. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48412 91177308-0d34-0410-b5e6-96231b3b80d8
2008-03-13Get rid of a pseudo instruction and replace it with subreg based operation ↵Christopher Lamb
on real instructions, ridding the asm printers of the hack used to do this previously. In the process, update LowerSubregs to be careful about eliminating copies that have side affects. Note: the coalescer will have to be careful about this too, when it starts coalescing insert_subreg nodes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48329 91177308-0d34-0410-b5e6-96231b3b80d8
2008-03-11Recommitting parts of r48130. These do not appear to cause the observed ↵Christopher Lamb
failures. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48223 91177308-0d34-0410-b5e6-96231b3b80d8
2008-03-11Use TargetRegisterInfo::getPhysicalRegisterRegClass. Remove duplicated code.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48221 91177308-0d34-0410-b5e6-96231b3b80d8
2008-03-10Revert 48125, 48126, and 48130 for now to unbreak some x86-64 tests.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48167 91177308-0d34-0410-b5e6-96231b3b80d8
2008-03-10Allow insert_subreg into implicit, target-specific values. Christopher Lamb
Change insert/extract subreg instructions to be able to be used in TableGen patterns. Use the above features to reimplement an x86-64 pseudo instruction as a pattern. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48130 91177308-0d34-0410-b5e6-96231b3b80d8
2008-02-10Rename MRegisterInfo to TargetRegisterInfo.Dan Gohman
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46930 91177308-0d34-0410-b5e6-96231b3b80d8
2007-12-31Move copyRegToReg from MRegisterInfo to TargetInstrInfo. This is part of theOwen Anderson
Machine-level API cleanup instigated by Chris. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45470 91177308-0d34-0410-b5e6-96231b3b80d8
2007-12-31Rename SSARegMap -> MachineRegisterInfo in keeping with the idea Chris Lattner
that "machine" classes are used to represent the current state of the code being compiled. Given this expanded name, we can start moving other stuff into it. For now, move the UsedPhysRegs and LiveIn/LoveOuts vectors from MachineFunction into it. Update all the clients to match. This also reduces some needless #includes, such as MachineModuleInfo from MachineFunction. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45467 91177308-0d34-0410-b5e6-96231b3b80d8
2007-12-29Remove attribution from file headers, per discussion on llvmdev.Chris Lattner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45418 91177308-0d34-0410-b5e6-96231b3b80d8
2007-10-23isSubRegOf() is a dup of isSubRegister.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@43249 91177308-0d34-0410-b5e6-96231b3b80d8
2007-09-26Allow copyRegToReg to emit cross register classes copies.Evan Cheng
Tested with "make check"! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@42346 91177308-0d34-0410-b5e6-96231b3b80d8
2007-09-14Remove isReg, isImm, and isMBB, and change all their users to use Dan Gohman
isRegister, isImmediate, and isMachineBasicBlock, which are equivalent, and more popular. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@41958 91177308-0d34-0410-b5e6-96231b3b80d8
2007-08-10Move isSubRegOf into MRegisterInfo. Fix a missed move elimination in ↵Christopher Lamb
LowerSubregs and add more debugging output there. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@41005 91177308-0d34-0410-b5e6-96231b3b80d8
2007-08-06Implement review feedback. No functionality change.Christopher Lamb
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40863 91177308-0d34-0410-b5e6-96231b3b80d8
2007-07-26Add a MachineFunction pass, which runs post register allocation, that turns ↵Christopher Lamb
subreg insert/extract instruction into register copies. This ensures correct code gen if the coalescer isn't able to remove all subreg instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40521 91177308-0d34-0410-b5e6-96231b3b80d8
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