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2012-05-01Merging r155902:Bill Wendling
------------------------------------------------------------------------ r155902 | void | 2012-05-01 01:27:43 -0700 (Tue, 01 May 2012) | 7 lines Change the PassManager from a reference to a pointer. The TargetPassManager's default constructor wants to initialize the PassManager to 'null'. But it's illegal to bind a null reference to a null l-value. Make the ivar a pointer instead. PR12468 ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_31@155903 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-23Merging r155288:Bill Wendling
------------------------------------------------------------------------ r155288 | d0k | 2012-04-21 09:05:27 -0700 (Sat, 21 Apr 2012) | 6 lines Remove unused PointerLikeTypeTraits for IndexListEntry. It set NumLowBitAvailable = 3 which may not be true on all platforms. We only ever use 2 bits (the default) so this assumption can be safely removed Should fix PR12612. ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_31@155375 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-18This reverts a long string of commits to the Hexagon backend. TheseChandler Carruth
commits have had several major issues pointed out in review, and those issues are not being addressed in a timely fashion. Furthermore, this was all committed leading up to the v3.1 branch, and we don't need piles of code with outstanding issues in the branch. It is possible that not all of these commits were necessary to revert to get us back to a green state, but I'm going to let the Hexagon maintainer sort that out. They can recommit, in order, after addressing the feedback. Reverted commits, with some notes: Primary commit r154616: HexagonPacketizer - There are lots of review comments here. This is the primary reason for reverting. In particular, it introduced large amount of warnings due to a bad construct in tablegen. - Follow-up commits that should be folded back into this when reposting: - r154622: CMake fixes - r154660: Fix numerous build warnings in release builds. - Please don't resubmit this until the three commits above are included, and the issues in review addressed. Primary commit r154695: Pass to replace transfer/copy ... - Reverted to minimize merge conflicts. I'm not aware of specific issues with this patch. Primary commit r154703: New Value Jump. - Primarily reverted due to merge conflicts. - Follow-up commits that should be folded back into this when reposting: - r154703: Remove iostream usage - r154758: Fix CMake builds - r154759: Fix build warnings in release builds - Please incorporate these fixes and and review feedback before resubmitting. Primary commit r154829: Hexagon V5 (floating point) support. - Primarily reverted due to merge conflicts. - Follow-up commits that should be folded back into this when reposting: - r154841: Remove unused variable (fixing build warnings) There are also accompanying Clang commits that will be reverted for consistency. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155047 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-17Unbreak the MSVC build, that next() thing again.Francois Pichet
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154916 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-17SlotIndexes used to store the index list in a crufty custom linked-list. I can'tLang Hames
for the life of me remember why I wrote it this way, but I can't see any good reason for it now. This patch replaces the custom linked list with an ilist. This change should preserve the existing numberings exactly, so no generated code should change (if it does, file a bug!). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154904 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-13misched: Added CanHandleTerminators.Andrew Trick
This is a special flag for targets that really want their block terminators in the DAG. The default scheduler cannot handle this correctly, so it becomes the specialized scheduler's responsibility to schedule terminators. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154712 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-12HexagonPacketizer patch.Sirish Pande
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154616 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-10Fix a long standing tail call optimization bug. When a libcall is emittedEvan Cheng
legalizer always use the DAG entry node. This is wrong when the libcall is emitted as a tail call since it effectively folds the return node. If the return node's input chain is not the entry (i.e. call, load, or store) use that as the tail call input chain. PR12419 rdar://9770785 rdar://11195178 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154370 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-09Typo.Eric Christopher
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154329 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-04Always compute all the bits in ComputeMaskedBits.Rafael Espindola
This allows us to keep passing reduced masks to SimplifyDemandedBits, but know about all the bits if SimplifyDemandedBits fails. This allows instcombine to simplify cases like the one in the included testcase. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154011 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-03Matrix simplification in PBQP may push infinite costs onto register options.Lang Hames
The colorability heuristic should count these as denied registers. No test case - this exposed a bug on an out-of-tree target. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153958 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-03Fixes to r153903. Added missing explanation of behaviour when the ↵Pete Cooper
VirtRegMap is NULL. Also changed it in this case to just avoid updating the map, but live ranges or intervals will still get updated and created git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153914 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-02Moved LiveRangeEdit.h so that it can be called from other parts of the ↵Pete Cooper
backend, not just libCodeGen git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153906 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-01misched: Add finalizeScheduler to complete the target interface.Andrew Trick
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153827 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-31Teach CodeGen's version of computeMaskedBits to understand the range metadata.Rafael Espindola
This is the CodeGen equivalent of r153747. I tested that there is not noticeable performance difference with any combination of -O0/-O2 /-g when compiling gcc as a single compilation unit. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153817 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-28Enable machine code verification in the entire code generator.Jakob Stoklund Olesen
Some targets still mess up the liveness information, but that isn't verified after MRI->invalidateLiveness(). The verifier can still check other useful things like register classes and CFG, so it should be enabled after all passes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153615 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-27Add an MRI::tracksLiveness() flag.Jakob Stoklund Olesen
Late optimization passes like branch folding and tail duplication can transform the machine code in a way that makes it expensive to keep the register liveness information up to date. There is a fuzzy line between register allocation and late scheduling where the liveness information degrades. The MRI::tracksLiveness() flag makes the line clear: While true, liveness information is accurate, and can be used for register scavenging. Once the flag is false, liveness information is not accurate, and can only be used as a hint. Late passes generally don't need the liveness information, but they will sometimes use the register scavenger to help update it. The scavenger enforces strict correctness, and we have to spend a lot of code to update register liveness that may never be used. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153511 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-26Add a debug option to dump PBQP graphs during register allocation.Lang Hames
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153483 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-17MachineInstr: Inline the fast path (non-bundle instruction) of hasProperty.Benjamin Kramer
This is particularly helpful as both arguments tend to be constants. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152991 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-16Limit the number of memory operands in MachineInstr to 2^16 and store the ↵Benjamin Kramer
number in padding. Saves one machine word on MachineInstr (88->80 bytes on x86_64, 48->44 on i386). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152930 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-16Revert r152613 (and r152614), "Inline the d'tor and add an anchor instead." ↵NAKAMURA Takumi
for workaround of g++-4.4's miscompilation. It caused MSP430DAGToDAGISel::SelectIndexedBinOp() to be miscompiled. When two ReplaceUses()'s are expanded as inline, vtable in base class is stored to latter (ISelUpdater)ISU. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152877 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-14misched: implemented a framework for top-down or bottom-up scheduling.Andrew Trick
New flags: -misched-topdown, -misched-bottomup. They can be used with the default scheduler or with -misched=shuffle. Without either topdown/bottomup flag -misched=shuffle now alternates scheduling direction. LiveIntervals update is unimplemented with bottom-up scheduling, so only -misched-topdown currently works. Capped the ScheduleDAG hierarchy with a concrete ScheduleDAGMI class. ScheduleDAGMI is aware of the top and bottom of the unscheduled zone within the current region. Scheduling policy can be plugged into the ScheduleDAGMI driver by implementing MachineSchedStrategy. ConvergingScheduler is now the default scheduling algorithm. It exercises the new driver but still does no reordering. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152700 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-13s/SjLjEHPass/SjLjEHPrepare/Bill Wendling
No functionality change. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152658 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-13Inline the d'tor and add an anchor instead.Bill Wendling
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152613 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-11Convert more static tables of registers used by calling convention to ↵Craig Topper
uint16_t to reduce space. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152538 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-09misched interface: rename Begin/End to RegionBegin/RegionEnd since they are ↵Andrew Trick
not private. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152382 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-09misched: allow the default scheduler to be one chosen by the target.Andrew Trick
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152360 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-09Added TargetPassConfig::enablePassAndrew Trick
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152359 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-08misched interface: Expose the MachineScheduler pass.Andrew Trick
Allow targets to provide their own schedulers (subclass of ScheduleDAGInstrs) to the misched pass. Select schedulers using -misched=... git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152278 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-07Cleanup VLIWPacketizer to use the updated ScheduleDAGInstrs interface.Andrew Trick
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152262 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-07misched prep: Expose the ScheduleDAGInstrs interface so targets mayAndrew Trick
implement their own MachineScheduler. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152261 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-07misched preparation: rename core scheduler methods for consistency.Andrew Trick
We had half the API with one convention, half with another. Now was a good time to clean it up. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152255 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-07misched preparation: clarify ScheduleDAG and ScheduleDAGInstrs roles.Andrew Trick
ScheduleDAG is responsible for the DAG: SUnits and SDeps. It provides target hooks for latency computation. ScheduleDAGInstrs extends ScheduleDAG and defines the current scheduling region in terms of MachineInstr iterators. It has access to the target's scheduling itinerary data. ScheduleDAGInstrs provides the logic for building the ScheduleDAG for the sequence of MachineInstrs in the current region. Target's can implement highly custom schedulers by extending this class. ScheduleDAGPostRATDList provides the driver and diagnostics for current postRA scheduling. It maintains a current Sequence of scheduled machine instructions and logic for splicing them into the block. During scheduling, it uses the ScheduleHazardRecognizer provided by the target. Specific changes: - Removed driver code from ScheduleDAG. clearDAG is the only interface needed. - Added enterRegion/exitRegion hooks to ScheduleDAGInstrs to delimit the scope of each scheduling region and associated DAG. They should be used to setup and cleanup any region-specific state in addition to the DAG itself. This is necessary because we reuse the same ScheduleDAG object for the entire function. The target may extend these hooks to do things at regions boundaries, like bundle terminators. The hooks are called even if we decide not to schedule the region. So all instructions in a block are "covered" by these calls. - Added ScheduleDAGInstrs::begin()/end() public API. - Moved Sequence into the driver layer, which is specific to the scheduling algorithm. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152208 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-07misched preparation: modularize schedule emission.Andrew Trick
ScheduleDAG has nothing to do with how the instructions are scheduled. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152206 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-07misched preparation: modularize schedule printing.Andrew Trick
ScheduleDAG will not refer to the scheduled instruction sequence. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152205 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-07misched preparation: modularize schedule verification.Andrew Trick
ScheduleDAG will not refer to the scheduled instruction sequence. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152204 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-07Cleanup in preparation for misched: Move DAG visualization logic.Andrew Trick
Soon, ScheduleDAG will not refer to the BB. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152177 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-07Added MachineBasicBlock::getFullName() to standardize/factor codegen ↵Andrew Trick
diagnostics. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152176 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-07Cleanup: DAG building is specific to either SD or MI scheduling. Not part of ↵Andrew Trick
the target interface. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152174 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-07misched commentsAndrew Trick
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152173 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-05Remove an unused function.Nadav Rotem
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152028 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-04Use <def,undef> operands when spilling NEON bundles.Jakob Stoklund Olesen
MachineOperands that define part of a virtual register must have an <undef> flag if they are not intended as read-modify-write operands. The old trick of adding an <imp-def> operand doesn't work any longer. Fixes PR12177. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152008 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-04Use uint16_t to store register overlaps to reduce static data.Craig Topper
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152001 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-02delete dead code, patch by Michael Spencer.Jia Liu
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151909 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-01Make InlineSpiller bundle-aware.Jakob Stoklund Olesen
Simply treat bundles as instructions. Spill code is inserted between bundles, never inside a bundle. Rewrite all operands in a bundle at once. Don't attempt and memory operand folding inside bundles. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151787 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-01Move getBundleStart() into MachineInstrBundle.h.Jakob Stoklund Olesen
This allows the function to be inlined, and makes it suitable for use in getInstructionIndex(). Also provide a const version. C++ is great for touch typing practice. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151782 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-29Add an analyzeVirtReg() function.Jakob Stoklund Olesen
This function does more or less the same as MI::readsWritesVirtualRegister(), but it supports bundles as well. It also determines if any constraint requires reading and writing operands to use the same register. Most clients want to know. Use the more modern MO.readsReg() instead of trying to sort out undefs and partial redefines. Stop supporting the extra full <imp-def> operand as an alternative to <def,undef> sub-register defines. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151690 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-29Move the operand iterator into MachineInstrBundle.h where it belongs.Jakob Stoklund Olesen
Extract a base class and provide four specific sub-classes for iterating over const/non-const bundles/instructions. This eliminates the mystery bool constructor argument. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151684 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-28Instructions inside a bundle have the same number as the bundle itself.Jakob Stoklund Olesen
SlotIndexes are not assigned to instructions inside bundles, but it is still valid to look up the index of those instructions. The reverse getInstructionFromIndex() will return the first instruction in the bundle. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151672 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-27Add a MachineOperand iterator class.Jakob Stoklund Olesen
The MIOperands iterator can visit operands on a single instruction, or all operands in a bundle. This simplifies code like the register allocator that treats bundles as a set of operands. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151529 91177308-0d34-0410-b5e6-96231b3b80d8
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