aboutsummaryrefslogtreecommitdiff
AgeCommit message (Collapse)Author
2013-04-10Revert "TMP"Tim Northover
This reverts commit e652085eacbec62e4157d08d3f2f875e6e6d5bb4. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179172 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-10ARM: Make "SMC" instructions conditional on new TrustZone architecture feature.Tim Northover
These instructions aren't universally available, but depend on a specific extension to the normal ARM architecture (rather than, say, v6/v7/...) so a new feature is appropriate. This also enables the feature by default on A-class cores which usually have these extensions, to avoid breaking existing code and act as a sensible default. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179171 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-10TMPTim Northover
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179170 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-10Change CloneFunctionInto to always clone Argument attributes induvidually,Joey Gouly
rather than checking if the source and destination have the same number of arguments and copying the attributes over directly. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179169 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-10R600/SI: dynamical figure out the reg class of MIMGChristian Konig
Depending on the number of bits set in the writemask. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179166 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-10R600/SI: adjust writemask to only the used componentsChristian Konig
Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179165 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-10R600/SI: remove image sample writemaskChristian Konig
Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179164 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-10Cleanup PPCInstrInfo::DefinesPredicateHal Finkel
Implement suggestions made by Bill Schmidt in post-commit review. Thanks! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179162 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-10RegionInfo: Add helpers to replace entry/exit recursivelyTobias Grosser
Contributed by: Star Tan <tanmx_star@yeah.net> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179157 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-10PPC: Prep for if conversion of bctr[l]Hal Finkel
This adds in-principle support for if-converting the bctr[l] instructions. These instructions are used for indirect branching. It seems, however, that the current if converter will never actually predicate these. To do so, it would need the ability to hoist a few setup insts. out of the conditionally-executed block. For example, code like this: void foo(int a, int (*bar)()) { if (a != 0) bar(); } becomes: ... beq 0, .LBB0_2 std 2, 40(1) mr 12, 4 ld 3, 0(4) ld 11, 16(4) ld 2, 8(4) mtctr 3 bctrl ld 2, 40(1) .LBB0_2: ... and it would be safe to do all of this unconditionally with a predicated beqctrl instruction. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179156 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-10Template the MachO types over endianness.Rafael Espindola
For now they are still only used as little endian. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179147 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-10Include the more specific header.Rafael Espindola
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179146 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-10__sincosf_stret returns sinf / cosf in bits 0:31 and 32:63 of xmm0, not inEvan Cheng
xmm0 / xmm1. rdar://13599493 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179141 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-10Generalize the PassConfig API and remove addFinalizeRegAlloc().Andrew Trick
The target hooks are getting out of hand. What does it mean to run before or after regalloc anyway? Allowing either Pass* or AnalysisID pass identification should make it much easier for targets to use the substitutePass and insertPass APIs, and create less need for badly named target hooks. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179140 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-09Mips specific inline asm operand modifier 'D' Jack Carter
Modifier 'D' is to use the second word of a double integer. We had previously implemented the pure register varient of the modifier and this patch implements the memory reference. #include "stdio.h" int b[8] = {0,1,2,3,4,5,6,7}; void main() { int i; // The first word. Notice, no 'D' {asm ( "lw %0,%1;" : "=r" (i) : "m" (*(b+4)) );} printf("%d\n",i); // The second word {asm ( "lw %0,%D1;" : "=r" (i) : "m" (*(b+4)) );} printf("%d\n",i); } git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179135 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-09Allow PPC B and BLR to be if-converted into some predicated formsHal Finkel
This enables us to form predicated branches (which are the same conditional branches we had before) and also a larger set of predicated returns (including instructions like bdnzlr which is a conditional return and loop-counter decrement all in one). At the moment, if conversion does not capture all possible opportunities. A simple example is provided in early-ret2.ll, where if conversion forms one predicated return, and then the PPCEarlyReturn pass picks up the other one. So, at least for now, we'll keep both mechanisms. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179134 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-09Fix some comment typos.Bob Wilson
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179132 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-09Cleanup. No functional change intended.Chad Rosier
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179129 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-09Cleanup. No functional change intended.Chad Rosier
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179125 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-09Remove unused method and default values.Rafael Espindola
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179124 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-09Update the version of dwarf we say we're emitting to at least 3.Eric Christopher
Deals with a dwarf2 -> dwarf3 DW_FORM_ref_addr change. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179122 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-09Revert r179115 as it looks to have killed the ASan tests.Chad Rosier
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179120 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-09Rationalize the formatting of these case labels. Having two sortedChandler Carruth
columns is essentially impossible to edit. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179119 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-09This patch enables llvm to switch between compiling for mips32/mips64 Reed Kotler
and mips16 on a per function basis. Because this patch is somewhat involved I have provide an overview of the key pieces of it. The patch is written so as to not change the behavior of the non mixed mode. We have tested this a lot but it is something new to switch subtargets so we don't want any chance of regression in the mainline compiler until we have more confidence in this. Mips32/64 are very different from Mip16 as is the case of ARM vs Thumb1. For that reason there are derived versions of the register info, frame info, instruction info and instruction selection classes. Now we register three separate passes for instruction selection. One which is used to switch subtargets (MipsModuleISelDAGToDAG.cpp) and then one for each of the current subtargets (Mips16ISelDAGToDAG.cpp and MipsSEISelDAGToDAG.cpp). When the ModuleISel pass runs, it determines if there is a need to switch subtargets and if so, the owning pointers in MipsTargetMachine are appropriately changed. When 16Isel or SEIsel is run, they will return immediately without doing any work if the current subtarget mode does not apply to them. In addition, MipsAsmPrinter needs to be reset on a function basis. The pass BasicTargetTransformInfo is substituted with a null pass since the pass is immutable and really needs to be a function pass for it to be used with changing subtargets. This will be fixed in a follow on patch. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179118 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-09Add support for bottom-up SLP vectorization infrastructure.Nadav Rotem
This commit adds the infrastructure for performing bottom-up SLP vectorization (and other optimizations) on parallel computations. The infrastructure has three potential users: 1. The loop vectorizer needs to be able to vectorize AOS data structures such as (sum += A[i] + A[i+1]). 2. The BB-vectorizer needs this infrastructure for bottom-up SLP vectorization, because bottom-up vectorization is faster to compute. 3. A loop-roller needs to be able to analyze consecutive chains and roll them into a loop, in order to reduce code size. A loop roller does not need to create vector instructions, and this infrastructure separates the chain analysis from the vectorization. This patch also includes a simple (100 LOC) bottom up SLP vectorizer that uses the infrastructure, and can vectorize this code: void SAXPY(int *x, int *y, int a, int i) { x[i] = a * x[i] + y[i]; x[i+1] = a * x[i+1] + y[i+1]; x[i+2] = a * x[i+2] + y[i+2]; x[i+3] = a * x[i+3] + y[i+3]; } git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179117 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-09Make check depend on all.Eric Christopher
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179116 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-09[ms-inline asm] Use parsePrimaryExpr in lieu of parseExpression if we need toChad Rosier
parse an identifier. Otherwise, parseExpression may parse multiple tokens, which makes it impossible to properly compute an immediate displacement. An example of such a case is the source operand (i.e., [Symbol + ImmDisp]) in the below example: __asm mov eax, [Symbol + ImmDisp] The existing test cases exercise this patch. rdar://13611297 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179115 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-09The .dwo section shouldn't contain the unrelocated values (andEric Christopher
therefore not at all) of the pc or statement list. We also don't need to emit the compilation dir so save so space and time and don't bother. Fix up the testcase accordingly and verify that we don't emit the attributes or the items that they use. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179114 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-09Cleanup PPCEarlyReturnHal Finkel
Some general cleanup and only scan the end of a BB for branches (once we're done with the terminators and debug values, then there should not be any other branches). These address post-commit review suggestions by Bill Schmidt. No functionality change intended. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179112 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-09Revert r176408 and r176407 to address PR15540.Nadav Rotem
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179111 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-09[ms-inline asm] Maintain a StringRef to reference a symbol in a parsed operand,Chad Rosier
rather than deriving the StringRef from the Start and End SMLocs. Using the Start and End SMLocs works fine for operands such as [Symbol], but not for operands such as [Symbol + ImmDisp]. All existing test cases that reference a variable exercise this patch. rdar://13602265 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179109 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-09DAGCombiner: Fold a shuffle on CONCAT_VECTORS into a new CONCAT_VECTORS if ↵Benjamin Kramer
possible. This pattern occurs in SROA output due to the way vector arguments are lowered on ARM. The testcase from PR15525 now compiles into this, which is better than the code we got with the old scalarrepl: _Store: ldr.w r9, [sp] vmov d17, r3, r9 vmov d16, r1, r2 vst1.8 {d16, d17}, [r0] bx lr Differential Revision: http://llvm-reviews.chandlerc.com/D647 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179106 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-09Use virtual base registers on PPCHal Finkel
On PowerPC, non-vector loads and stores have r+i forms; however, in functions with large stack frames these were not being used to access slots far from the stack pointer because such slots were out of range for the signed 16-bit immediate offset field. This increases register pressure because we need a separate register for each offset (when the r+r form is used). By enabling virtual base registers, we can deal with large stack frames without unduly increasing register pressure. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179105 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-09Convert test PowerPC/2007-09-07-LoadStoreIdxForms to FileCheckHal Finkel
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179104 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-09Rewrite test/Linker tests to use FileCheck instead of grep.Eli Bendersky
Some translations here are not 1x1 because there are grep|grep chains that are non-trivial to implement in terms of FileCheck features. I made an effort for the tests to remain as similar as possible; do let me know if you notice anything fishy. The good news are that some buggy tests were fixed (grep | not grep - a bug waiting to happen). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179102 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-09Convert MachOObjectFile to a template.Rafael Espindola
For now it is templated only on being 64 or 32 bits. I will add little/big endian next. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179097 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-09DWARF parser: Fix DWARF-2/3 incompatibility: size of DW_FORM_ref_addr is the ↵Alexey Samsonov
same as DW_FORM_addr in DWARF2, and is 4/8 bytes on 32/64-bit DWARF starting from DWARF3. Adding a test for this is a huge pain - generating and uploading pre-built binary with DWARF3 debug info is way too ugly, and writing fine-grained unittests for DebugInfo is impossible, as it doesn't expose any headers in include/llvm. That said, I'm going to choose the second approach and submit the patch exposing DebugInfo headers for review soon enough. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179095 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-09Converted 8x tests of SimplifyCFG to use FileCheck instead of grep.Michael Gottesman
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179087 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-09Extract a function.Jakob Stoklund Olesen
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179086 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-09Remove the confusing sentence.Nadav Rotem
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179085 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-09Revert 179071 because it is not the right way to support non standard ↵Nadav Rotem
new/new[] operators. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179084 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-09Compute correct frame sizes for SPARC v9 64-bit frames.Jakob Stoklund Olesen
The save area is twice as big and there is no struct return slot. The stack pointer is always 16-byte aligned (after adding the bias). Also eliminate the stack adjustment instructions around calls when the function has a reserved stack frame. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179083 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-09More uses for SymbolTableEntryBase.Rafael Espindola
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179076 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-09Add a SymbolTableEntryBase.Rafael Espindola
Use it when we don't need to know if we have a 32 or 64 bit SymbolTableEntry. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179074 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-09Fix PointerIntPair to be enum class compatible.Joe Groff
Some parts of PointerIntPair assumed that the IntType of the pair was implicitly convertible to intptr_t, which is not the case for enum class values. Add a static_cast<intptr_t> to make these conversions explicit and allow PointerIntPair to be used with an enum class IntType. While we're here, rename some of the argument values so we don't have variables named "Int" floating around. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179073 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-08Add a SectionBase struct.Rafael Espindola
Use it to share code and when we don't need to know if we have a 32 or 64 bit Section. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179072 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-08c++ new operators are not malloc-like functions because they do not return ↵Nadav Rotem
uninitialized memory. Users may overide new-operators and implement any function that they like. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179071 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-08InstructionSimplify.cpp: Fix a ligature, "fi", to get rid of utf8 in comment.NAKAMURA Takumi
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179066 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-08Redo the fix Benjamin Kramer committed in r178793 about iterator ↵Shuxin Yang
invalidation in Reassociate. I brazenly think this change is slightly simpler than r178793 because: - no "state" in functor - "OpndPtrs[i]" looks simpler than "&Opnds[OpndIndices[i]]" While I can reproduce the probelm in Valgrind, it is rather difficult to come up a standalone testing case. The reason is that when an iterator is invalidated, the stale invalidated elements are not yet clobbered by nonsense data, so the optimizer can still proceed successfully. Thank Benjamin for fixing this bug and generously providing the test case. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179062 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-08Update the docs about the fact that the loop vectorizer is enabled by ↵Nadav Rotem
default for -O3. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179060 91177308-0d34-0410-b5e6-96231b3b80d8
generated by cgit v1.2.3-18-g5258 (git 2.32.0) at 2025-05-14 08:21:56 +0000