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metadata is the loop vectorizer.
See the documentation update for more info.
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via -print-after-all.
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This happens when there is both stack realignment and a dynamic alloca in the
function. If we overwrite %esi (rep;movsl uses fixed registers) we'll lose the
base pointer and the next register spill will write into oblivion.
Fixes PR15249 and unbreaks firefox on i386/freebsd. Mozilla uses dynamic allocas
and freebsd a 4 byte stack alignment.
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#cmakedefine does not behave the way I though it was.
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since a caller uses preserved registers across the call.
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of the assignment with the same condition.
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assembly.
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thanks to David Blaike for pointing this out.
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RegisterCoalescer used to depend on LiveDebugVariable. LDV removes DBG_VALUEs
without emitting them at the end.
We fix this by removing LDV from RegisterCoalescer. Also add an assertion to
make sure we call emitDebugValues if DBG_VALUEs are removed at
runOnMachineFunction.
rdar://problem/13183203
Reviewed by Andy & Jakob
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rdar://13202662
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visitSExt is an adapted copy of the related visitZExt method, so adapt the comment accordingly.
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trying to do.
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.align).
Also, allow _EMIT and __EMIT for the emit directive. We already do the same
for TYPE, SIZE, and LENGTH.
rdar://13200215
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violations such as tabs, blanks at eol and long
lines.
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function is called with a signed char argument, in order to avoid assertions in Windows Debug configuration.
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avoid a second pred_iterator traversal.
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(through a loop), don't continue to iterate through the reamining
predecessors.
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for tidiness' sake.
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This is complicated by backward labels (e.g., 0b can be both a backward label
and a binary zero). The current implementation assumes [0-9]b is always a
label and thus it's possible for 0b and 1b to not be interpreted correctly for
ms-style inline assembly. However, this is relatively simple to fix in the
inline assembly (i.e., drop the [bB]).
This patch also limits backward labels to [0-9]b, so that only 0b and 1b are
ambiguous.
Part of rdar://12470373
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option "generate-dwarf-pubnames" to control it, set to "false" by default.
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MI sched DAG construction allows targets to include terminators into scheduling DAG.
Extend this functionality to labels as well.
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Patch by: Kevin Schoedel
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instructions.
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DAGCombiner::ReduceLoadWidth was converting (trunc i32 (shl i64 v, 32))
into (shl i32 v, 32) into undef. To prevent this, check the shift count
against the final result size.
Patch by: Kevin Schoedel
Reviewed by: Nadav Rotem
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Vectors were being manually scalarized by the backend. Instead,
let the target-independent code do all of the work. The manual
scalarization was from a time before good target-independent support
for scalarization in LLVM. However, this forces us to specially-handle
vector loads and stores, which we can turn into PTX instructions that
produce/consume multiple operands.
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may get mapped at 0x100000000+ and thus may interleave with the shadow.
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'R600/SI: Use proper instructions for array/shadow samplers.' removed two
cases from TEX_SHADOW. Vincent Lejeune reported on IRC that this broke some
shadow array piglit tests with the r600g driver. Reinstating the removed
cases should fix this, and still works with radeonsi as well.
I will follow up with some lit tests which would have caught the regression.
NOTE: This is a candidate for the Mesa stable branch.
Tested-by: Vincent Lejeune <vljn@ovi.com>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
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This is based on Bill Wendling's email. No additional content has been added,
but now there's a place for Attributes to capture future information.
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roughly 5% speedup. Since this is an ABI change, bump the asan ABI version by renaming __asan_init to __asan_init_v1. llvm part, compiler-rt part will follow
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