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2013-03-05Hexagon: Add support for lowering block address.Jyotsna Verma
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176508 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-05R600: Do not predicate vector opVincent Lejeune
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176507 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-05Hexagon: Expand addc, adde, subc and sube.Jyotsna Verma
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176505 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-05Use the right number of slashes in comment stringArnold Schwaighofer
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176504 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-05Fixes a test by replacing .align by .p2align and setting triples explicitly.Eli Bendersky
Patch by David Sehr git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176502 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-05Update cmake build.Benjamin Kramer
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176501 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-05Hexagon: Use MO operand flags to mark constant extended instructions.Jyotsna Verma
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176500 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-05Hexagon: Add encoding bits to the TFR64 instructions.Jyotsna Verma
Set imMoveImm, isAsCheapAsAMove flags for TFRI instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176499 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-05R600: initial scheduler codeVincent Lejeune
This is a skeleton for a pre-RA MachineInstr scheduler strategy. Currently it only tries to expose more parallelism for ALU instructions (this also makes the distribution of GPR channels more uniform and increases the chances of ALU instructions to be packed together in a single VLIW group). Also it tries to reduce clause switching by grouping instruction of the same kind (ALU/FETCH/CF) together. Vincent Lejeune: - Support for VLIW4 Slot assignement - Recomputation of ScheduleDAG to get more parallelism opportunities Tom Stellard: - Fix assertion failure when trying to determine an instruction's slot based on its destination register's class - Fix some compiler warnings Vincent Lejeune: [v2] - Remove recomputation of ScheduleDAG (will be provided in a later patch) - Improve estimation of an ALU clause size so that heuristic does not emit cf instructions at the wrong position. - Make schedule heuristic smarter using SUnit Depth - Take constant read limitations into account Vincent Lejeune: [v3] - Fix some uninitialized values in ConstPair - Add asserts to ensure an ALU slot is always populated git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176498 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-05Clarify comment for function getObjectSizeArnold Schwaighofer
Clarify that we mean the object starting at the pointer to the end of the underlying object and not the size of the whole allocated object. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176491 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-05Add a test that .align directives on capable processors use long NOPs.David Sehr
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176490 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-05R600: Remove LowerConstCopyPass and lower CONST_COPY right after ISel.Vincent Lejeune
Maintaining CONST_COPY Instructions until Pre Emit may prevent some ifcvt case and taking them in account for scheduling is difficult for no real benefit. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176488 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-05R600: Turn BUILD_VECTOR into Reg_SequenceVincent Lejeune
Reviewed-by: Tom Stellard <thomas.stellard at amd.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176487 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-05R600: CONST_ADDRESS node is not marked as mayLoad anymoreVincent Lejeune
Reviewed-by: Tom Stellard <thomas.stellard at amd.com> mayLoad complexify scheduling and does not bring any usefull info as the location is not writeable at all. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176486 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-05R600: Use MUL_IEEE for trig/fdiv intrinsicVincent Lejeune
Reviewed-by: Tom Stellard <thomas.stellard at amd.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176485 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-05R600: Add support for indirect addressing of non default const bufferVincent Lejeune
NOTE: This is a candidate for the Mesa stable branch. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176484 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-05Print a warning message if compiler-rt can't be built because of old CMake ↵Alexey Samsonov
version to make this requirement more visible to users git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176481 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-05llvm/test/CodeGen/Mips/mips64-f128.ll: Add explicit ↵NAKAMURA Takumi
-mtriple=mips64el-unknown-unknown to appease win32. FIXME: Is it expected for win32 to affect mips targets? git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176471 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-05llvm/test/CodeGen/Thumb/iabs.ll: Add explicit -mtriple=thumb-unknown-unknown ↵NAKAMURA Takumi
to appease win32 hosts. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176470 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-05Remove unused #includes.Bill Wendling
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176467 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-05The current X86 NOP padding uses one long NOP followed by the remainder inDavid Sehr
one-byte NOPs. If the processor actually executes those NOPs, as it sometimes does with aligned bundling, this can have a performance impact. From my micro-benchmarks run on my one machine, a 15-byte NOP followed by twelve one-byte NOPs is about 20% worse than a 15 followed by a 12. This patch changes NOP emission to emit as many 15-byte (the maximum) as possible followed by at most one shorter NOP. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176464 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-04Check isDiscardableIfUnused, rather than hasLocalLinkage, when bumpingLang Hames
GlobalValue linkage up to ExternalLinkage in the ExtractGV pass. This prevents linkonce and linkonce_odr symbols from being DCE'd. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176459 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-04[mips] Print move instructions.Akira Hatanaka
"move $4, $5" is printed instead of "or $4, $5, $zero". git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176455 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-04Mips specific inline assembler constraint 'R'Jack Carter
'R' An address that can be sued in a non-macro load or store. This patch includes a positive test case. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176452 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-04Reapply r176381, writing the CHECKs in a more forgiving manner to account forEli Bendersky
running llvm-objdump on Darwin. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176443 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-04Bypass Slow DividesPreston Gurd
* Only apply divide bypass optimization when not optimizing for size. * Fixed bug caused by constant for 0 value of type Int32, used dividend type to generate the constant instead. * For atom x86-64 apply the divide bypass to use 16-bit divides instead of 64-bit divides when operand values are small enough. * Added lit tests for 64-bit divide bypass. Patch by Tyler Nowicki! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176442 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-04R600: Clean up datalayout strings so they better match hardware capabilitiesTom Stellard
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176439 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-04Mips ISD typoJia Liu
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176426 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-02ARM: Creating a vector from a lane of another.Jim Grosbach
The VDUP instruction source register doesn't allow a non-constant lane index, so make sure we don't construct a ARM::VDUPLANE node asking it to do so. rdar://13328063 http://llvm.org/bugs/show_bug.cgi?id=13963 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176413 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-02Clean up code format a bit.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176412 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-02Tidy up. Trailing whitespace.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176411 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-02ARM NEON: Fix v2f32 float intrinsicsArnold Schwaighofer
Mark them as expand, they are not legal as our backend does not match them. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176410 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-02recommit r172363 & r171325 (reverted in r172756)Nuno Lopes
This adds minimalistic support for PHI nodes to llvm.objectsize() evaluation fingers crossed so that it does break clang boostrap again.. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176408 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-02add getUnderlyingObjectSize()Nuno Lopes
this is similar to getObjectSize(), but doesnt subtract the offset tweak the BasicAA code accordingly (per PR14988) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176407 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-02X86 cost model: Adjust cost for custom lowered vector multipliesArnold Schwaighofer
This matters for example in following matrix multiply: int **mmult(int rows, int cols, int **m1, int **m2, int **m3) { int i, j, k, val; for (i=0; i<rows; i++) { for (j=0; j<cols; j++) { val = 0; for (k=0; k<cols; k++) { val += m1[i][k] * m2[k][j]; } m3[i][j] = val; } } return(m3); } Taken from the test-suite benchmark Shootout. We estimate the cost of the multiply to be 2 while we generate 9 instructions for it and end up being quite a bit slower than the scalar version (48% on my machine). Also, properly differentiate between avx1 and avx2. On avx-1 we still split the vector into 2 128bits and handle the subvector muls like above with 9 instructions. Only on avx-2 will we have a cost of 9 for v4i64. I changed the test case in test/Transforms/LoopVectorize/X86/avx1.ll to use an add instead of a mul because with a mul we now no longer vectorize. I did verify that the mul would be indeed more expensive when vectorized with 3 kernels: for (i ...) r += a[i] * 3; for (i ...) m1[i] = m1[i] * 3; // This matches the test case in avx1.ll and a matrix multiply. In each case the vectorized version was considerably slower. radar://13304919 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176403 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-02Added FIXME for future Hexagon cleanup.Andrew Trick
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176400 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-02PR14448 - prevent the loop vectorizer from vectorizing the same loop twice.Nadav Rotem
The LoopVectorizer often runs multiple times on the same function due to inlining. When this happens the loop vectorizer often vectorizes the same loops multiple times, increasing code size and adding unneeded branches. With this patch, the vectorizer during vectorization puts metadata on scalar loops and marks them as 'already vectorized' so that it knows to ignore them when it sees them a second time. PR14448. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176399 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-02Modify {Call,Invoke}Inst::addAttribute to take an AttrKind.Peter Collingbourne
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176397 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-02CMake: Always include the CheckCXXCompilerFlag in HandleLLVMOptions.cmake.Jordan Rose
Previously we relied on it being included by config-ix.cmake. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176396 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-02Revert "Rewrite a test to count emitted instructions without using -stats"Michael Gottesman
This reverts commit aac7922b8fe7ae733d3fe6697e6789fd730315dc. I am reverting the commit since it broke the phase 1 public buildbot for a few hours. http://lab.llvm.org:8013/builders/clang-x86_64-darwin11-nobootstrap-RA/builds/2137 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176394 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-01Remove duplicate line and move another closer to its actual useEli Bendersky
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176391 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-01MIsched machine model: tablegen subtarget emitter improvement.Andrew Trick
Fix the way resources are counted. I'm taking some time to cleanup the way MachineScheduler handles in-order machine resources. Eventually we'll need more PPC/Atom test cases in tree. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176390 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-01In llvm::MemoryBuffer::getFile() remove an unnecessary stat call check.Argyrios Kyrtzidis
The sys::fs::is_directory() check is unnecessary because, if the filename is a directory, the function will fail anyway with the same error code returned. Remove the check to avoid an unnecessary stat call. Someone needs to review on windows and see if the check is necessary there or not. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176386 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-01Fix my email address in CREDITS.TXT.Stefanus Du Toit
Checking to see if svn notifications also use correct address now. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176385 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-01[mips] Fix inefficient code generation.Akira Hatanaka
This patch eliminates the need to emit a constant move instruction when this pattern is matched: (select (setgt a, Constant), T, F) The pattern above effectively turns into this: (conditional-move (setlt a, Constant + 1), F, T) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176384 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-01Removed extraneous #include "LLVMContextImpl.h" from lib/IR/Module.cppJean-Luc Duprat
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176382 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-01Rewrite a test to count emitted instructions without using -statsEli Bendersky
Also removed the comments of "should produce..." because they completely don't match the actually produced output. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176381 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-01Fix indentation.Akira Hatanaka
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176380 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-01Set properties for f128 type.Akira Hatanaka
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176378 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-01Rewrite a test to check actual output rather than intermediate implementationEli Bendersky
detail. The was this test was written, it was relying on an implementation detail (fixups) and hence was very brittle (relying, among other things, on the exact ordering of statistics printed by MC). The test was rewritten to check a more observable output difference. While it doesn't cover 100% of the things the original test covered, it's a good practice to write regression tests this way. If we want to check that internal details and invariants hold, such tests should be expressed as unit tests. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176377 91177308-0d34-0410-b5e6-96231b3b80d8
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