aboutsummaryrefslogtreecommitdiff
AgeCommit message (Collapse)Author
2013-03-23Plug a memory leak in FileCheck when the input file is empty.Benjamin Kramer
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177822 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-23Move X86-dependent test into the right subdirectory.Benjamin Kramer
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177821 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-23Remove the type legality check from the SelectionDAGBuilder when it lowers ↵Owen Anderson
@llvm.fmuladd to ISD::FMA nodes. Performing this check unilaterally prevented us from generating FMAs when the incoming IR contained illegal vector types which would eventually be legalized to underlying types that *did* support FMA. For example, an @llvm.fmuladd on an OpenCL float16 should become a sequence of float4 FMAs, not float4 fmul+fadd's. NOTE: Because we still call the target-specific profitability hook, individual targets can reinstate the old behavior, if desired, by simply performing the legality check inside their callback hook. They can also perform more sophisticated legality checks, if, for example, some illegal vector types can be productively implemented as FMAs, but not others. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177820 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-23Change method name ClearRefCount => ClearKnownPositiveRefCount to match the ↵Michael Gottesman
name of the member that it is modifying. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177818 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-23Changed the method name PtrState.IsKnownIncremented() to ↵Michael Gottesman
PtrState.HasKnownPositiveRefCount(). Now said method matches namewise every other method which refers to the member KnownPositiveRefCount of the class PtrState. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177816 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-23Fix comparison of mixed signednessHal Finkel
177774 broke the lld-x86_64-darwin11 builder; error: error: comparison of integers of different signs: 'int' and 'size_type' (aka 'unsigned long') for (SI = 0; SI < Scavenged.size(); ++SI) ~~ ^ ~~~~~~~~~~~~~~~~ Fix this by making SI also unsigned. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177780 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-22[docs] Slight reword for precision.Sean Silva
The new wording cannot be construed as suggesting the use of SmallVectorImpl<T> as e.g. a class member (just because the class happens to be in an interface). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177778 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-22[docs] Document usage of SmallVectorImpl in interfaces.Sean Silva
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177775 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-22Allow the register scavenger to spill multiple registersHal Finkel
This patch lets the register scavenger make use of multiple spill slots in order to guarantee that it will be able to provide multiple registers simultaneously. To support this, the RS's API has changed slightly: setScavengingFrameIndex / getScavengingFrameIndex have been replaced by addScavengingFrameIndex / isScavengingFrameIndex / getScavengingFrameIndices. In forthcoming commits, the PowerPC backend will use this capability in order to implement the spilling of condition registers, and some special-purpose registers, without relying on r0 being reserved. In some cases, spilling these registers requires two GPRs: one for addressing and one to hold the value being transferred. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177774 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-22Support in AAEvaluator to print alias queries of loads/stores with TBAA tags.Manman Ren
Add "evaluate-tbaa" to print alias queries of loads/stores. Alias queries between pointers do not include TBAA tags. Add testing case for "placement new". TBAA currently says NoAlias. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177772 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-22Kill every call to @clang.arc.use in the ARC contract phase.John McCall
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177769 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-22Update test. There may be multiple catches, but those will be cleaned up.Bill Wendling
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177758 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-22Add all clauses when merging the landing pads. Duplicates will be handled ↵Bill Wendling
later on. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177757 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-22Swap the DIFile in DILexicalBlockFile out for the raw name/directory pairDavid Blaikie
This is the last change in transitioning all DIScopes to have a common prefix. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177756 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-22reorder the fields in DILexicalBlockFile to match the common prefix for DIScopesDavid Blaikie
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177754 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-22Reverted r176374. In some cases the lit.site.cfg file does not get generated ↵Galina Kistanova
in tools/clang/tools/extra. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177751 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-22Don't use the removed API.Bill Wendling
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177749 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-22Revert r177675. This is language-specific and shouldn't be in the API.Bill Wendling
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177748 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-22Hexagon: Add and enable memops setbit, clrbit, &,|,+,- for byte, short, and ↵Jyotsna Verma
word. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177747 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-22Refactor out the DIFile parameter to DILexicalBlock to refer to the raw ↵David Blaikie
file/directory pair git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177742 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-22fix small doc typoEli Bendersky
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177737 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-22R600: Fix up test/CodeGen/R600/llvm.pow.ll for r177730Michel Danzer
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177736 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-22Remove ABI-duplicated call instruction patterns.Ulrich Weigand
We currently have a duplicated set of call instruction patterns depending on the ABI to be followed (Darwin vs. Linux). This is a bit odd; while the different ABIs will result in different instruction sequences, the actual instructions themselves ought to be independent of the ABI. And in fact it turns out that the only nontrivial difference between the two sets of patterns is that in the PPC64 Linux ABI, the instruction used for indirect calls is marked to take X11 as extra input register (which is indeed used only with that ABI to hold an incoming environment pointer for nested functions). However, this does not need to be hard-coded at the .td pattern level; instead, the C++ code expanding calls can simply add that use, just like it adds uses for argument registers anyway. No change in generated code expected. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177735 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-22Rename memrr ptrreg and offreg components.Ulrich Weigand
Currently, the sub-operand of a memrr address that corresponds to what hardware considers the base register is called "offreg", while the sub-operand that corresponds to the offset is called "ptrreg". To avoid confusion, this patch simply swaps the named of those two sub-operands and updates all uses. No functional change is intended. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177734 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-22Fix swapped BasePtr and Offset in pre-inc memory addresses.Ulrich Weigand
PPCTargetLowering::getPreIndexedAddressParts currently provides the base part of a memory address in the offset result, and the offset part in the base result. That swap is then undone again when an MI instruction is generated (in PPCDAGToDAGISel::Select for loads, and using .md Pat patterns for stores). This patch reverts this double swap, to make common code and back-end be in sync as to which part of the address is base and which is offset. To avoid performance regressions in certain cases, target code now checks whether the choice of base register would be rejected for pre-inc accesses by common code, and attempts to swap base and offset again in such cases. (Overall, this means that now pre-ice accesses are generated *more* frequently than before.) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177733 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-22Tighten iaddroff ComplexPattern.Ulrich Weigand
The iaddroff ComplexPattern is supposed to recognize displacement expressions that have been processed by a SelectAddressRegImm, which means it needs to accept TargetConstant and TargetGlobalAddress nodes. Currently, it erroneously also accepts some other nodes, in particular Constant and PPCISD::Lo. While this problem is currently latent, it would cause wrong-code bugs with a follow-on patch I'm about to commit, so this patch tightens the ComplexPattern. The equivalent change is made in PPCDAGToDAGISel::Select, where pre-inc load patterns are handled (as opposed to store patterns, the loads are handled in C++ code without making use of the .td ComplexPattern). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177732 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-22Remove the xaddroff ComplexPattern.Ulrich Weigand
The xaddroff pattern is currently (mistakenly) used to recognize the *base* register in pre-inc store patterns. This patch replaces those uses by ptr_rc_nor0 (as is elsewhere done to match the base register of an address), and removes the now unused ComplexPattern. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177731 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-22R600: Use legacy (0 * anything = 0) MUL instructions for pow intrinsicsMichel Danzer
Fixes wrong lighting in some corner cases with r600g and radeonsi, e.g. manifested by failure of two piglit/glean tests and intermittent black patches in many apps. Tested on SI and RS880. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=62012 [radeonsi] Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=58150 [r600g] NOTE: This is a candidate for the Mesa stable branch. Reviewed-by: Christian König <christian.koenig@amd.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177730 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-22[asan] Change the way we report the alloca frame on stack-buff-overflow.Kostya Serebryany
Before: the function name was stored by the compiler as a constant string and the run-time was printing it. Now: the PC is stored instead and the run-time prints the full symbolized frame. This adds a couple of instructions into every function with non-empty stack frame, but also reduces the binary size because we store less strings (I saw 2% size reduction). This change bumps the asan ABI version to v3. llvm part. Example of report (now): ==31711==ERROR: AddressSanitizer: stack-buffer-overflow on address 0x7fffa77cf1c5 at pc 0x41feb0 bp 0x7fffa77cefb0 sp 0x7fffa77cefa8 READ of size 1 at 0x7fffa77cf1c5 thread T0 #0 0x41feaf in Frame0(int, char*, char*, char*) stack-oob-frames.cc:20 #1 0x41f7ff in Frame1(int, char*, char*) stack-oob-frames.cc:24 #2 0x41f477 in Frame2(int, char*) stack-oob-frames.cc:28 #3 0x41f194 in Frame3(int) stack-oob-frames.cc:32 #4 0x41eee0 in main stack-oob-frames.cc:38 #5 0x7f0c5566f76c (/lib/x86_64-linux-gnu/libc.so.6+0x2176c) #6 0x41eb1c (/usr/local/google/kcc/llvm_cmake/a.out+0x41eb1c) Address 0x7fffa77cf1c5 is located in stack of thread T0 at offset 293 in frame #0 0x41f87f in Frame0(int, char*, char*, char*) stack-oob-frames.cc:12 <<<<<<<<<<<<<< this is new This frame has 6 object(s): [32, 36) 'frame.addr' [96, 104) 'a.addr' [160, 168) 'b.addr' [224, 232) 'c.addr' [288, 292) 's' [352, 360) 'd' git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177724 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-22tsan: fix the testDmitry Vyukov
Add missed file from r177717 commit that adds __tsan_vptr_read. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177719 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-22tsan: handle vptr loads speciallyDmitry Vyukov
This is required to determine ctor/dtor vs virtual call races. http://llvm-reviews.chandlerc.com/D566 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177717 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-22Fix llvm::removeUnreachableBlocks to handle unreachable loops.Evgeniy Stepanov
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177713 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-22InstCombine: Improve the result bitvect type when folding (cmp pred (load ↵Arnaud A. de Grandmaison
(gep GV, i)) C) to a bit test. The original code used i32, and i64 if legal. This introduced unneeded casts when they aren't legal, or when the index variable i has another type. In order of preference: try to use i's type; use the smallest fitting legal type (using an added DataLayout method); default to i32. A testcase checks that this works when the index gep operand is i16. Patch by : Ahmed Bougacha <ahmed.bougacha@gmail.com> Reviewed by : Duncan git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177712 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-22Remove ScavengedRC from RegisterScavengingHal Finkel
ScavengedRC was a dead private variable (set, but not otherwise used). No functionality change intended. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177708 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-22Reorder the DIFile field in DILexicalBlock to become a prefix common with ↵David Blaikie
other DIScopes git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177703 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-22Remove the empty directory. Silly git-svn.Chandler Carruth
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177702 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-22Remove the ARM-specific variant of this test. It's already covered byChandler Carruth
the ARM build bots, and it adds a weird case to the test suite where a test uses as inputs files in the parent directory. Talked about this with Dave on IRC and he's fine with this approach even though it isn't optimal. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177700 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-22Introduce LLVM_STATIC_ASSERT macro, which expands to C/C++'s static_assert ↵Argyrios Kyrtzidis
on compilers which support it. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177699 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-22Revert r177543: Add timing of the IR parsing code with a newChandler Carruth
-time-ir-parsing flag This breaks the layering of the Support library. We can't add an implementation side to IRReader because it refers directly to entities only accessible as part of the IR, AsmParser, and BitcodeReader libraries. It can only be used in a context where all of those libraries will be available. We'll need to find some other way to get this functionality, and hopefully solve the long-standing layering problem of IRReader.h... git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177695 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-22Fix the invalid opcode for Mips branch instructions in the assemblerJack Carter
For mips a branch an 18-bit signed offset (the 16-bit offset field shifted left 2 bits) is added to the address of the instruction following the branch (not the branch itself), in the branch delay slot, to form a PC-relative effective target address. Previously, the code generator did not perform the shift of the immediate branch offset which resulted in wrong instruction opcode. This patch fixes the issue. Contributor: Vladimir Medic git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177687 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-22This patch that enables the Mips assembler to use symbols for offset for ↵Jack Carter
instructions This patch uses the generated instruction info tables to identify memory/load store instructions. After successful matching and based on the operand type and size, it generates additional instructions to the output. Contributor: Vladimir Medic git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177685 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-21Remove the G8RC_NOX0_and_GPRC_NOR0 PPC register classHal Finkel
As Jakob pointed out in his review of r177423, having a shared ZERO register between the 32- and 64-bit register classes causes this odd G8RC_NOX0_and_GPRC_NOR0 class to be created. As recommended, this adds a ZERO8 register which differentiates the 32- and 64-bit zeros. No functionality change intended. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177683 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-21Add TableGen ctags(1) emitter and helper script.Sean Silva
To use this in conjunction with exuberant ctags to generate a single combined tags file, run tblgen first and then $ ctags --append [...] Since some identifiers have corresponding definitions in C++ code, it can be useful (if using vim) to also use cscope, and :set cscopetagorder=1 so that :tag X will preferentially select the tablegen symbol, while :cscope find g X will always find the C++ symbol. Patch by Kevin Schoedel! (a couple small formatting changes courtesy of clang-format) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177682 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-21Always forward 'resume' instructions to the outter landing pad.Bill Wendling
How did this ever work? Basically, if you have a function that's inlined into the caller, it may not have any 'call' instructions, but any 'resume' instructions it may have should still be forwarded to the outer (caller's) landing pad. This requires that all of the 'landingpad' instructions in the callee have their clauses merged with the caller's outer 'landingpad' instruction (hence the bit of ugly code in the `forwardResume' method). Testcase in a follow commit to the test-suite repository. <rdar://problem/13360379> & PR15555 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177680 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-21Fix a register-class comparison bug in PPCCTRLoopsHal Finkel
Thanks to Jakob for isolating the underlying problem from the test case in r177423. The original commit had introduced asymmetric copy operations, but these turned out to be a work-around to the real problem (the use of == instead of hasSubClassEq in PPCCTRLoops). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177679 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-21Refactor the filename/directory information in DISubprogram to refer ↵David Blaikie
directly to the pair rather than the DIFile. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177677 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-21Add a query to tell if a landing pad has a catch-all.Bill Wendling
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177675 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-21Move the DIFile in DISubprogram to the beginning to be a common prefix along ↵David Blaikie
with other DIScopes git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177674 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-21<rdar://problem/13477190> On Darwin, use DARWIN_USER_TEMP_DIR or ↵Douglas Gregor
DARWIN_USER_CACHE_DIR for the system temporary directory. The DARWIN_USER_TEMP_DIR and DARWIN_USER_CACHE_DIR configuration settings are more idiomatic for Darwin than the TMPDIR environment variable. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177669 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-21This patch enables the Mips .set directive to define aliasesJack Carter
The .set directive in the Mips the assembler can be used to set the value of a symbol to an expression. This changes the symbol's value and type to conform to the expression's. Syntax: .set symbol, expression This patch implements the parsing of the above syntax and enables the parser to use defined symbols when parsing operands. Contributor: Vladimir Medic git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177667 91177308-0d34-0410-b5e6-96231b3b80d8
generated by cgit v1.2.3-18-g5258 (git 2.32.0) at 2025-07-07 23:55:08 +0000