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2013-03-25Add an optimizer-side test case for ARC bug <rdar://13195034>, fixedJohn McCall
in the frontend with @clang.arc.use. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177928 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-25Couple more sets of tidying.Eric Christopher
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177920 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-25Disable profiling tests for Hexagon since it doesn't support JIT.Jyotsna Verma
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177917 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-25llvm/test/CodeGen/X86/atomic{32|64}.ll: Unmark them out of XFAIL:win32.NAKAMURA Takumi
I know it is incorrect and they'd fail with +Asserts for win32 targets, though. I'll try to fix them tonight. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177914 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-25XFAIL some of the generic CodeGen tests for Hexagon.Jyotsna Verma
test/CodeGen/Generic/2008-02-20-MatchingMem.ll: Test contains inline assembly not supported by Hexagon. Following tests are XFAILed due to multiple return values which Hexagon doesn't support. test/CodeGen/Generic/multiple-return-values-cross-block-with-invoke.ll test/CodeGen/Generic/select-cc.ll test/CodeGen/Generic/vector.ll git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177912 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-25X86DisassemblerDecoder.c: Make this C89-compliant.NAKAMURA Takumi
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177910 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-25Whitespace.NAKAMURA Takumi
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177909 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-25Fix a bug in fast-math fadd/fsub simplification. Shuxin Yang
The problem is that the code mistakenly took for granted that following constructor is able to create an APFloat from a *SIGNED* integer: APFloat::APFloat(const fltSemantics &ourSemantics, integerPart value) rdar://13486998 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177906 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-25[ELF] dont compute symbolname size in every loopShankar Easwaran
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177903 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-25XFAIL DebugInfo tests for Hexagon.Jyotsna Verma
Hexagon does not support -filetype=obj(direct object generation) flag. Therefore, the following tests are being XFAILed: test/DebugInfo/dwarf-public-names.ll test/DebugInfo/member-pointers.ll test/DebugInfo/two-cus-from-same-file.ll git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177901 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-25Fix comment.Akira Hatanaka
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177899 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-25Formatting.Eric Christopher
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177898 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-25Disable Execution Engine tests not supported by Hexagon.Jyotsna Verma
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177896 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-25reflect comment to the official referenceShankar Easwaran
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177895 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-25Disable, for now, llvm/test/Transforms/GCOVProfiling on win32. I'll ↵NAKAMURA Takumi
investigate them later. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177894 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-25Use direct types in PowerPC instruction patterns.Ulrich Weigand
This commit updates the PowerPC back-end (PPCInstrInfo.td and PPCInstr64Bit.td) to use types instead of register classes in instruction patterns, along the lines of Jakob Stoklund Olesen's changes in r177835 for Sparc. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177890 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-25Use direct types in PowerPC Pat patterns.Ulrich Weigand
This commit updates the PowerPC back-end (PPCInstrInfo.td and PPCInstr64Bit.td) to use types instead of register classes in Pat patterns, along the lines of Jakob Stoklund Olesen's changes in r177829 for Sparc. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177889 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-25x86 -- add the XTEST instructionDave Zarzycki
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177888 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-25x86 -- disassemble the REP/REPNE prefix when neededDave Zarzycki
This fixes Apple bug: 13493622 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177887 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-25Remove unnecessary attributes from test case.Chad Rosier
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177882 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-25Remove assert. There may be target-dependent attributes left.Bill Wendling
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177878 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-25Documentation: Replace dead link for binfmt_miscDmitri Gribenko
Patch by Thomas Schwinge. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177876 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-25[arm load/store optimizer] When trying to merge a base update load/store, makeChad Rosier
sure the base register and would-be writeback register don't conflict for stores. This was already being done for loads. Unfortunately, it is rather difficult to create a test case for this issue. It was exposed in 450.soplex at LTO and requires unlucky register allocation. <rdar://13394908> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177874 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-25[tools][llvm-readobj] print the name of the section when iterating the ↵Shankar Easwaran
symbol table / dynamic symbol table git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177873 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-25[ELF] add elf_hash function to compute the hash value of a symbol in the ↵Shankar Easwaran
dynamic symbol table git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177872 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-25Teach cmake about the new Erlang GC files.Duncan Sands
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177869 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-25Add a GC plugin for ErlangYiannis Tsiouris
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177867 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-25Don't use add_llvm_definitions for adding warning flags. It makes it too hardDuncan Sands
to have them appear in the right order. Instead append all warnings explicitly to the language flags. This was already the case for many warnings. Fixes the issue of -Wno-maybe-uninitialized not being effective because -Wall was being placed after it rather than before. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177866 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-25Refine fenv.h handling: check if the desired macros exist, before usingJoerg Sonnenberger
it. NetBSD/ARM and TILE-Gx are examples for platforms that have an unusable fenv.h and this avoids the need for a blacklist. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177865 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-25Address issues found by Duncan during post-commit review of r177856.Arnaud A. de Grandmaison
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177863 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-25InstCombine: simplify comparisons to zero of (shl %x, Cst) or (mul %x, Cst)Arnaud A. de Grandmaison
This simplification happens at 2 places : - using the nsw attribute when the shl / mul is used by a sign test - when the shl / mul is compared for (in)equality to zero git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177856 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-25Changed isNullOrUndef => IsNullOrUndef and isNoopInstruction => ↵Michael Gottesman
IsNoopInstruction so that all helper functions are named similarly in ObjCARC.h. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177855 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-25Mention the new TableGen pattern format in the release notes.Jakob Stoklund Olesen
Make threats about removing the old syntax. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177848 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-24[NVPTX] Fix handling of vector argumentsJustin Holewinski
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177847 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-24Clean up Sparc patterns.Jakob Stoklund Olesen
The types of register variables no longer need to be specified in output patterns. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177845 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-24Allow types to be omitted in output patterns.Jakob Stoklund Olesen
This syntax is now preferred: def : Pat<(subc i32:$b, i32:$c), (SUBCCrr $b, $c)>; There is no reason to repeat the types in the output pattern. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177844 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-24Allow TableGen DAG arguments to be just a name.Jakob Stoklund Olesen
DAG arguments can optionally be named: (dag node, node:$name) With this change, the node is also optional: (dag node, node:$name, $name) The missing node is treated as an UnsetInit, so the above is equivalent to: (dag node, node:$name, ?:$name) This syntax is useful in output patterns where we currently require the types of variables to be repeated: def : Pat<(subc i32:$b, i32:$c), (SUBCCrr i32:$b, i32:$c)>; This is preferable: def : Pat<(subc i32:$b, i32:$c), (SUBCCrr $b, $c)>; git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177843 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-24GettingStarted: Add Git clone instructions for compiler-rt and test-suiteTobias Grosser
Contributed-by: Thomas Schwinge <thomas@codesourcery.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177841 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-24Minor cleanups. No functionality change.Jakub Staszak
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177837 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-24Use dyn_cast instead of isa && cast.Jakub Staszak
No functionality change. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177836 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-24Give Sparc instruction patterns direct types instead of register classes.Jakob Stoklund Olesen
Also update the documentation since Sparc is the nicest backend, and used as an example in WritingAnLLVMBackend. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177835 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-24Allow direct value types to be used in instruction 'set' patterns.Jakob Stoklund Olesen
This makes it possible to define instruction patterns like this: def LDri : F3_2<3, 0b000000, (outs IntRegs:$dst), (ins MEMri:$addr), "ld [$addr], $dst", [(set i32:$dst, (load ADDRri:$addr))]>; ~~~ git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177834 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-23PPC ZERO register needs a register number of 0.Hal Finkel
In order for the new ZERO register to be used with MC, etc. we need to specify its register number (0). Thanks to Kai for reporting the problem! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177833 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-23Note in PPCFunctionInfo VRSAVE spillsHal Finkel
In preparation for using the new register scavenger capability for providing more than one register simultaneously, specifically note functions that have spilled VRSAVE (currently, this can happen only in functions that use the setjmp intrinsic). As with CR spilling, such functions will need to provide two emergency spill slots to the scavenger. No functionality change intended. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177832 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-23MCize the bcl instruction in PPCAsmPrinterHal Finkel
I recently added a BCL instruction definition as part of implementing SjLj support. This can also be used to MCize bcl emission in the asm printer. No functionality change intended. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177830 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-23Use direct types in Sparc def : Pat patterns.Jakob Stoklund Olesen
The SelectionDAG graph has MVT type labels, not register classes, so this makes it clearer what is happening. This notation is also robust against adding more types to the IntRegs register class. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177829 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-23Allow direct value types in pattern definitions.Jakob Stoklund Olesen
Just like register classes, value types can be used in two ways in patterns: (sext_inreg i32:$src, i16) In a named leaf node like i32:$src, the value type simply provides the type of the node directly. This simplifies type inference a lot compared to the current practice of specifiying types indirectly with register classes. As an unnamed leaf node, like i16 above, the value type represents itself as an MVT::Other immediate. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177828 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-23Cleanup some unused reg. scavenger parameters in PPCRegisterInfoHal Finkel
These spilling functions will eventually make use of the register scavenger, however, they'll do so by taking advantage of PEI's virtual-register-based delayed scavenging mechanism. As a result, these function parameters will not be used, and can be removed. No functionality change intended. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177827 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-23Make all unnamed RegisterClass TreePatternNodes typed MVT::i32.Jakob Stoklund Olesen
A register class can appear as a leaf TreePatternNode with and without a name: (COPY_TO_REGCLASS GPR:$src, F8RC) In a named leaf node like GPR:$src, the register class provides type information for the named variable represented by the node. The TypeSet for such a node is the set of value types that the register class can represent. In an unnamed leaf node like F8RC above, the register class represents itself as a kind of immediate. Such a node has the type MVT::i32, we'll never create a virtual register representing it. This change makes it possible to remove the special handling of COPY_TO_REGCLASS in CodeGenDAGPatterns.cpp. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177825 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-23Remove dead PPC LR spilling codeHal Finkel
The LR register is unconditionally reserved, and its spilling and restoration is handled by the prologue/epilogue code. As a result, it is never explicitly spilled by the register allocator. No functionality change intended. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177823 91177308-0d34-0410-b5e6-96231b3b80d8
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