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2010-11-01Covert this test to .s form.Owen Anderson
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117937 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-01Add FIXME.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117936 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-01Covert this test to .s form.Owen Anderson
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117935 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-01Fix test.Rafael Espindola
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117932 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-01Add 'IsThumb' predicate to patterns marked as 'IsThumb1Only'. The latter gatesJim Grosbach
codegen using the patterns; the latter gates the assembler recognizing the instruction. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117931 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-01Write the line info to .debug_line.Rafael Espindola
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117930 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-01Mark ARM subtarget features that are available for the assembler.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117929 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-01trailing whitespaceJim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117927 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-01Move EmitInstruction to MCObjectStreamer so that ELF and MachO can share it.Rafael Espindola
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117925 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-01The T2 extract/pack instructions are only valid in Thumb2 mode. Mark theJim Grosbach
patterns as such git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117923 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-01Add support for .value.Rafael Espindola
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117922 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-01Implement .weakref.Rafael Espindola
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117911 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-01Move instruction encoding bits into the parent class and remove the temporaryBill Wendling
*_Encode classes. These instructions are the only ones which use those classes, so a subclass isn't necessary. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117906 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-01More tests to XFAIL. The arm-and-txt-peephole.ll test passes even when theBill Wendling
peephole optimizer is disabled. That's not good at all. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117905 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-01The testcase is now XFAILed. Sorry about the breakage.Bill Wendling
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117904 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-01Disable because peephole is disabled.Bill Wendling
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117903 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-01"mov[zs]x (mem), GR16" are not ambiguous: the memChris Lattner
must be 8 bits. Support this memory form. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117902 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-01Implement enough of the missing instalias support to getChris Lattner
aliases installed and working. They now work when the matched pattern and the result instruction have exactly the same operand list. This is now enough for us to define proper aliases for movzx and movsx, implementing rdar://8017633 and PR7459. Note that we do not accept instructions like: movzx 0(%rsp), %rsi GAS accepts this instruction, but it doesn't make any sense because we don't know the size of the memory operand. It could be 8/16/32 bits. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117901 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-01Convert this test to .s form.Owen Anderson
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117900 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-01rename InstructionInfo -> MatchableInfo since it nowChris Lattner
represents InstAliases as well. Rename isAssemblerInstruction -> Validate since that is what it does (modulo the ARM $lane hack). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117899 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-01refactor initialization of InstructionInfo to be sharable betweenChris Lattner
instructions and InstAliases. Start creating InstructionInfo's for Aliases. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117898 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-01make the asm matcher emitter reject instructions that have commentsChris Lattner
in their asmstring. Fix the two x86 "NOREX" instructions that have them. If these comments are important, the instlowering stuff can print them. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117897 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-01refactor InstructionInfo to not have a pointer to CodeGenInstructionChris Lattner
member, and make isAssemblerInstruction() a method (pushing some code around inside it). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117895 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-01define a new CodeGenInstAlias. It has an asmstring and operand list for now,Chris Lattner
todo: the result field. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117894 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-01factor the operand list (and related fields/operations) out of Chris Lattner
CodeGenInstruction into its own helper class. No functionality change. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117893 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-01avoid needless throw/catch/rethrow, stringref'ize some simple stuff.Chris Lattner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117892 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-01eliminate the old InstFormatName which is always "AsmString",Chris Lattner
simplify CodeGenInstruction. No functionality change. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117891 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-01all predicates on an MnemonicAlias must be AssemblerPredicates.Chris Lattner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117890 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-01change the singleton register handling code to be based on Record*'sChris Lattner
instead of strings, simplifying it. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117889 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-01Give AsmMatcherInfo a CodeGenTarget, which simplifies a bunch ofChris Lattner
argument passing. Consolidate all SingletonRegister detection and handling into a new InstructionInfo::getSingletonRegisterForToken method instead of having it scattered about. No change in generated .inc files. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117888 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-01move FlattenVariants out of AsmMatcherEmitter into a sharedChris Lattner
CodeGenInstruction::FlattenAsmStringVariants method. Use it to simplify the code in AsmWriterInst, which now no longer needs to worry about variants. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117886 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-01add a FIXME, $lane in ARM is an issue that needs to be resolved beforeChris Lattner
this can start rejecting instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117885 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-01reject instructions that contain a \n in their asmstring. MarkChris Lattner
various X86 and ARM instructions that are bitten by this as isCodeGenOnly, as they are. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117884 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-31Add a specialization for 'long', a hole in the set of fundamentalChandler Carruth
specializations provided here. This is a little annoying because its size changes from platform to platform. If possible, I may follow up with a patch that uses standard constants to simplify much of this, but assuming for now that was avoided for a reason. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117880 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-31Revert r117876 for now, it's causing more testsuite failures.Eric Christopher
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117879 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-31Disable the peephole optimizer until 186.crafty on armv6 is fixed. This is whatBill Wendling
looks like is happening: Without the peephole optimizer: (1) sub r6, r6, #32 orr r12, r12, lr, lsl r9 orr r2, r2, r3, lsl r10 (x) cmp r6, #0 ldr r9, LCPI2_10 ldr r10, LCPI2_11 (2) sub r8, r8, #32 (a) movge r12, lr, lsr r6 (y) cmp r8, #0 LPC2_10: ldr lr, [pc, r10] (b) movge r2, r3, lsr r8 With the peephole optimizer: ldr r9, LCPI2_10 ldr r10, LCPI2_11 (1*) subs r6, r6, #32 (2*) subs r8, r8, #32 (a*) movge r12, lr, lsr r6 (b*) movge r2, r3, lsr r8 (1) is used by (x) for the conditional move at (a). (2) is used by (y) for the conditional move at (b). After the peephole optimizer, these the flags resulting from (1*) are ignored and only the flags from (2*) are considered for both conditional moves. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117876 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-31Attach a GCModuleInfo to a MachineFunction.Nicolas Geoffray
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117867 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-31fix a crash on:Chris Lattner
let Constraints = "$val = $dst", Defs = [EFLAGS] in, isCodeGenOnly = 1 { we now get: X86InstrCompiler.td:653:52: error: Expected class, def, defm, multiclass or let definition let Constraints = "$val = $dst", Defs = [EFLAGS] in, isCodeGenOnly = 1 { ^ git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117863 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-31fix the !eq operator in tblgen to return a bit instead of an int.Chris Lattner
Use this to make the X86 and ARM targets set isCodeGenOnly=1 automatically for their instructions that have Format=Pseudo, resolving a hack in tblgen. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117862 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-31two changes: make the asmmatcher generator ignore ARM pseudos properly,Chris Lattner
and make it a hard error for instructions to not have an asm string. These instructions should be marked isCodeGenOnly. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117861 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-31reapply r117858 with apparent editor malfunction fixed (somehow I Chris Lattner
got a dulicated line). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117860 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-31revert r117858 while I check out a failure I missed.Chris Lattner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117859 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-31the asm matcher can't handle operands with modifiers (like ${foo:bar}).Chris Lattner
Instead of silently ignoring these instructions, emit a hard error and force the target author to either refactor the target or mark the instruction 'isCodeGenOnly'. Mark a few instructions in ARM and MBlaze as isCodeGenOnly the are doing this. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117858 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-31sketch out the planned instruction alias mechanism, add some comments aboutChris Lattner
how the push/pop mnemonic aliases are wrong. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117857 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-31Factorize the duplicated logic for choosing the right argumentDuncan Sands
calling convention out of the fast and normal ISel files, and into the calling convention TD file. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117856 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-31Remove CCAssignFnForRet from X86 FastISel in favour of RetCC_X86,Duncan Sands
which has the same logic specified in the CallingConv TD file. This brings FastISel in line with the standard X86 ISel. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117855 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-31Explain the return value of CCAssignFn.Duncan Sands
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117854 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-31Add support for files with more than 65280 sections. No testcase sinceRafael Espindola
it would be a bit too big :-) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117849 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-30Make sure we have a legal type (and simple) before continuing.Eric Christopher
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117848 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-30Validate HTML.Benjamin Kramer
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117847 91177308-0d34-0410-b5e6-96231b3b80d8
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