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2011-09-12Port more encoding tests to decoding tests, and correct an improper Thumb2 ↵Owen Anderson
pre-indexed load decoding this uncovered. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139522 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-12Removing indvars tests that directly test canonical IVs and nothing else.Andrew Trick
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139518 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-12Rename -disable-iv-rewrite to -enable-iv-rewrite=false in preparation for ↵Andrew Trick
default change. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139517 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-12Add asserts to keep front-ends honest while encoding debug info into LLVM IR ↵Devang Patel
using DIBuilder. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139515 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-12Fix mistake in test runline.Eli Friedman
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139505 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-12Test case for r139453, WidenIV::GetExtendedOperandRecurrence.Andrew Trick
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139504 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-12Add DW_ATE_UTF, which clang started using in my previous commit!Devang Patel
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139503 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-12Remove the -compact-regions flag.Jakob Stoklund Olesen
It has been enabled by default for a while, it was only there to allow performance comparisons. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139501 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-12Add an interface for SplitKit complement spill modes.Jakob Stoklund Olesen
SplitKit always computes a complement live range to cover the places where the original live range was live, but no explicit region has been allocated. Currently, the complement live range is created to be as small as possible - it never overlaps any of the regions. This minimizes register pressure, but if the complement is going to be spilled anyway, that is not very important. The spiller will eliminate redundant spills, and hoist others by making the spill slot live range overlap some of the regions created by splitting. Stack slots are cheap. This patch adds the interface to enable spill modes in SplitKit. In spill mode, SplitKit will assume that the complement is going to spill, so it will allow it to overlap regions in order to avoid back-copies. By doing some of the spiller's work early, the complement live range becomes simpler. In some cases, it can become much simpler because no extra PHI-defs are required. This will speed up both splitting and spilling. This is only the interface to enable spill modes, no implementation yet. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139500 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-12Update comments to reflect some (not so) recent changes.Jakob Stoklund Olesen
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139498 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-12Associate a MemOperand with LDWCP nodes introduced during ISel.Richard Osborne
This information is required if we want LDWCP to be hoisted out of loops. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139495 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-12Mark LDWCP as having no side effects.Richard Osborne
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139494 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-12Format patterns, remove unused X86blend patternsNadav Rotem
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139491 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-11Fix disassembling of one of the register/register forms of ↵Craig Topper
MOVUPS/MOVUPD/MOVAPS/MOVAPD/MOVSS/MOVSD and their VEX equivalents. Fixes PR10877. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139486 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-11Fix disassembling of reverse register/register forms of ↵Craig Topper
ADD/SUB/XOR/OR/AND/SBB/ADC/CMP/MOV. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139485 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-11Fix disassembling of PAUSE instruction. Fixes PR10900. Also fixed NOP ↵Craig Topper
disassembling to ignore OpSize and REX.W. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139484 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-11s/SequeuentiallyConsistent/SequentiallyConsistent/gNick Lewycky
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139481 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-11Fix verb tense agreement.Nick Lewycky
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139480 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-11CR fixes per Bruno's request.Nadav Rotem
Undo the changes from r139285 which added custom lowering to vselect. Add tablegen lowering for vselect. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139479 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-10Really un-XFAIL the testcase, like I said I would in r139458.Eli Friedman
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139459 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-10r139454 activates an assert in a case where we were doing the right thing ↵Eli Friedman
anyway. Make that explicit, and un-XFAIL the testcase. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139458 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-10Fix the asserts in lib/Target/X86/X86ELFWriterInfo.cpp andRichard Trieu
lib/ExecutionEngine/MCJIT/MCJIT.cpp from: assert("error"); to: assert(0 && "error"); git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139456 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-10Fixed an assert from:Richard Trieu
assert("not implemented for target shuffle node"); to: assert(0 && "not implemented for target shuffle node"); This causes a test failure in CodeGen/X86/palignr.ll which has been marked as XFAIL for the time being. Test failure filed at PR10901. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139454 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-10[disable-iv-rewrite] Allow WidenIV to handle NSW/NUW operationsAndrew Trick
better. Don't immediately give up when an add operation can't be trivially sign/zero-extended within a loop. If it has NSW/NUW flags, generate a new expression with sign extended (non-recurrent) operand. As before, if SCEV says that all sign extends are loop invariant, then we can widen the operation. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139453 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-10Set NSW/NUW flags on SCEVAddExpr when the operation is flagged asAndrew Trick
such. I'm doing this now for completeness because I can't think of/remember any reason that it was left out. I'm not sure it will help anything, but if we don't do it we need to explain why in comments. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139450 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-10Fix asserts in CodeGen from:Richard Trieu
assert("error"); to: assert(0 && "error"); git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139449 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-10Thumb2 parsing and encoding for MOV(immediate).Jim Grosbach
Some aliases for MOV(register) also to keep existing T1 tests happy when run in thumbv7 mode. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139440 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-09Fix test cases.Akira Hatanaka
Generate code for Mips32r1 unless a Mips32r2 feature is tested. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139433 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-09LDM writeback is not allowed if Rn is in the target register list.Owen Anderson
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139432 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-09Fix an ambiguously nested if.Owen Anderson
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139431 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-09Fix buildbot breakage caused by r139415. I missed one instance of a ↵Owen Anderson
manually create ARM::tB. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139429 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-09Fix assembly/disassembly of Thumb2 ADR instructions with immediate operands.Owen Anderson
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139422 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-09O64 will not be supported.Akira Hatanaka
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139421 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-09Make F31 and D15 non-reserved registers.Akira Hatanaka
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139420 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-09tidy up a bitChris Lattner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139419 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-09Thumb unconditional branches are allowed in IT blocks, and therefore should ↵Owen Anderson
have a predicate operand, unlike conditional branches. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139415 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-09Update Clang AST attribute reader tblgen generation to match with ASTReader ↵Douglas Gregor
change git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139414 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-09Mips32 does not reserve even-numbered floating point registers.Akira Hatanaka
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139412 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-09Make the SelectionDAG verify that all the operands of BUILD_VECTOR have the ↵Eli Friedman
same type. Teach DAGCombiner::visitINSERT_VECTOR_ELT not to make invalid BUILD_VECTORs. Fixes PR10897. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139407 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-09Drop support for Mips1 and Mips2.Akira Hatanaka
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139405 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-09Implement vector-select support for avx256. Refactor the vblend ↵Nadav Rotem
implementation to have tablegen match the instruction by the node type git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139400 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-09Thumb2 assembly parsing and encoding for MLA and MLS.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139399 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-09Don't tack "Instruction not interpretable yet!" onto the end ofDuncan Sands
the instruction. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139398 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-09Thumb2 assembly parsing and encoding for MCR, MCR2, MCRR, MCRR2.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139397 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-09Tidy up formatting a bit.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139396 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-09Thumb2 assembly parsing and encoding for LSL.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139395 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-09Thumb2 assembly parsing and encoding for LDRT.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139393 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-09Thumb2 assembly parsing and encoding for LDRSHT.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139392 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-09Thumb2 assembly parsing and encoding for LDRSH.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139391 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-09Thumb2 assembly parsing and encoding for LDRSBT.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139390 91177308-0d34-0410-b5e6-96231b3b80d8
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